Fpga Control Register; Fpga Lock Register - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual
BASE+1E0
BASE+1C0
BASE+1A0
BASE+180
BASE+160
BASE+140
BASE+120
BASE+100
BASE+80
BASE+60
BASE+40
BASE+20
BASE+00

FPGA Control Register

Register Bit
Number
7
6
5
4
3
2
1
0
Hex value
3
2
1
0

FPGA Lock Register

Register Bit
Number
7
6
5
4
7-30
Crystal AES TX global chip select (used for synchronized TX reset)
Board I.D. register (read only, hardwired to $33)
Bit 1 of encoded source for slot word clock
Bit 0 of encoded source for slot word clock
Bit 1 of encoded source for preview word clock
Bit 0 of encoded source for preview word clock
Slot word clock output enable
Preview word clock output enable
Double speed mode
Local loopback mode (for test only)
Selected Word Clock Source
Crystal AES TX #4
Crystal AES TX #3
Crystal AES TX #2
Crystal AES TX #1
Crystal AES RX #4
Crystal AES RX #3
Crystal AES RX #2
Crystal AES RX #1
Octal Select Register
Lock Register
FPGA Control Register
Function
output
output
output
output
AES input #4
AES input #3
AES input #2
AES input #1
Function
(not used)
(not used)
(not used)
(not used)
Active State
See following
table
See following
table
See following
table
See following
table
High
High
High
High
Active State
-
-
-
-