Lexicon 960L Service Manual page 129

1000 0702
1800 0000 – 1800 0002
2000 0000 – 2000 FFFF
2800 0000 – 2800 FFFF
2C00 0000 – 2C00 FFFF
3000 0000 – 3000 FFFF
3800 0000 – 3800 FFFF
3C00 0000 – 3C00 FFFF
8000 0000
8000 0004
8000 0008
8000 000C
8000 0010
8000 0014
8000 0018
8000 001C
8000 0020
8000 0028
8001 0000
8001 0004
8001 0008
8001 000C
8001 0014
8001 001C
8001 0020
8002 0060
8002 0064
8002 0068
8002 006C
8002 0070
8002 0078
8002 0080
8002 0084
8003 0000
8003 0004
8003 0008
8003 000C
8003 0010
8003 0014
8003 001C
8003 0020
8004 0060
8004 0064
PS/2STAT PS/2 Status Register
CS3REG CS3 Register
PCMCIA socket 1 I/O space
PCMCIA socket 1 attribute space
PCMCIA socket 1 memory space
PCMCIA socket 2 I/O space
PCMCIA socket 2 attribute space
PCMCIA socket 2 Memory space
UDCCR UDC control register
UDCAR UDC address register
UDCOMP UDC OUT max packet register
UDCIMP UDC IN max packet register
UDCCS0 UDC endpoint 0 cntl/status reg
UDCCS1 UDC endpoint 1 cntl/status register
UDCCS2 UDC endpoint2 cntl/status register
UDCD0 UDC endpoint 0 data register
UDCWC UDC endpoint 0 write count register
UDCDR UDC xmit/rec data register (fifo)
UT1CR0 UART 1 control register 0
UT1CR1 UART 1 control register 1
UT1CR2 UART 1 control register 2
UT1CR3 UART 1 control register 3
UT1DR UART 1 data register
UT1SR0 UART 1 status register 0
UT1SR1 UART 1 status register 1
SDCR0 SDLC control register 0
SDCR1 SDLC control register 1
SDCR2 SDLC control register 2
SDCR3 SDLC control register 3
SDCR4 SDLC control register 4
SDDR SDLC data register
SDSR0 SDLC status register 0
SDSR1 SDLC status register 1
UT2CR0 UART 2 control register 0
UT2CR1 UART 2 control register 1
UT2CR2 UART 2 control register 2
UT2CR3 UART 2 control register 3
UT2CR4 UART 2 control register 4
UT2DR UART 2 data register
UT2SR0 UART 2 status register 0
UT2SR1 UART 2 status register 1
HSCR0 HSSP control register 0
HSCR1 HSSP control register 1
Lexicon
7-51