Pll Detailed Description - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual
divided by two, if necessary, to form single-speed wordclock from double-speed input. A final multiplexer
chooses the reference source to be applied to the PFD logic. When neither crystal oscillator is in use, they
both get disabled under software control by bringing XTAL_EN low. Multiplexing and other configuration of
the logic within U2 is established according to the value written to the internal control register by software.

PLL Detailed Description

To ensure a high degree of VCO stability and constant loop gain, 5Vdc for the PLL (5VA) is supplied by a
dedicated regulator, U7 (78L05), regulated from 12V. Diodes D5,D6 prevent large differences from existing
between the 5V supplies. Within the PLL, 5VA is decoupled at multiple points with ferrites and bypass
capacitors.
Phase-Frequency Detector
The PFD implemented within CPLD U2 is a well-known edge-detector type which compares the phase and
frequency of two logic signals and detects zero error at zero phase. Here the PFD inputs are the selected
reference wordclock and the single-speed wordclock derived from the VCO, both of which exist internal to
the CPLD. If the VCO frequency is too low or too high, the PFD drives output pins of the CPLD with a train
of mutually exclusive PUMP_UP or PUMP_DOWN/ pulses, respectively. As the VCO frequency changes to
approach lock, one train of pulses of varying width is generated. When the frequencies are essentially
equal, the pulses depend on the phase error between the two wordclock-rate signals. If the wordclock from
the VCO lags the reference, due to approach from a lower frequency, PUMP_UP is generated, and
PUMP_DOWN/ remains inactive. The opposite is true when approaching from a higher frequency. In an
ideal PFD of this type, when the edges of the two wordclock waveforms within the CPLD are exactly in
phase, neither pulse would occur; the zero-error phase-lock condition occurs when the edges are
coincident. In the basic PFD, if the reference signal drops to zero frequency (i.e., is absent), the logic would
assert PUMP_DOWN/ constantly, to try to force the VCO frequency to zero to match the reference. To
prevent this, special logic in the PFD defeats PUMP_DOWN/ if the reference is lost, preventing the forced
rapid drop of VCO frequency. Pulses from the CPLD are buffered by inverting stage U8 and become the
UP/ and DOWN pulses fed to the active loop filter. U8 is supplied by the regulated 5V to clamp the pulses
to a constant amplitude, removing any fluctuations that may be present on the main logic supply.
Voltage Controlled Oscillator
VCO U10 oscillates at a frequency which depends on L1 (1 uH), C35 (10pF), and the capacitance of
varactor diode D7 (BB132). The output of U10 is around 700 mVp-p at a dc level of nearly 4V. This small
signal is amplified and buffered by U9 (74HCU04) to develop PLL_512FS, a suitable logic level to drive
CPLD U2. The oscillation frequency is normally in the range of 22 to 25MHz, and when in lock, oscillation
is at an exact multiple (256 or 512) of the reference wordclock frequency.
The capacitance of D7 varies with its reverse-bias voltage; D7 is the element that allows voltage to control
frequency. The anode of D7 is constant at about 1.7 V, established by the VREF pin of U10. The voltage at
the cathode of D7 controls the VCO frequency. A greater positive voltage increases the reverse bias,
reducing the capacitance and producing a higher VCO frequency. The network formed by R13, C24, FB8,
and C37 helps keep high-frequency noise from being introduced at the cathode of D7, to reduce
undesirable modulation of the VCO.
The range of oscillation for the VCO is from around 18 to 30 MHz, and control voltage is typically 4 to 6
volts when locked to 44.1 to 48kHz wordclocks (22.579 to 24.576 MHz).
Active Filter
Op-amp U6 (NJM4580) and associated circuitry form an integrator that serves as the active loop filter. The
non-inverting input of U6 is biased at 2.5V by R7 and R8, and bypassed to ground by C22. The feedback
capacitors C20 and C23 integrate the current introduced to the summing node by input resistors R9 and
R11. R9 connects to logic level UP/ through series diode D3, and R11 connects to DOWN through series
diode D4.
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