Analog Output Card; Overview; Circuit Description; D/A Converter - Lexicon 960L Service Manual

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Analog Output card

The Analog Output card consists of eight channels of D/A conversion and output circuitry (sheets 1-4), bus
interface fpga and connector (sheets 5,6) and on-board power conditioning (sheet 7). This card is plugged
into the IO backplane, which is accessed from the rear of the 960L chassis. The following system block
diagram highlights its place within the 960L system.

Overview

The basis for each channel of analog output is a single AD1853 sigma-delta D/A converter, which converts
24-bit serial digital audio at its I2S port to differential analog current. The AD1853 is a two-channel device,
applicable to conventional stereo conversion, but as applied in this design, the two channels are combined
to form a single channel in order to achieve improved overall performance. Within a single wordclock
period, the digital data pattern presented for the left channel is the inverse of the data for the right channel,
while the analog outputs are cross-connected. In this way, one differential current pair is formed which is
the in-phase sum of currents resulting from two simultaneous conversions. The differential current is
converted to a differential voltage by low-noise operational amplifier stages, which drive a differential-input
two-pole active filter stage. The unbalanced output of the filter is ac-coupled to the DRV134 differential
transformerless line driver, to deliver fullscale differential output at +24dBm to XLR connectors. A two-pole
muting relay prevents uncontrolled transients from appearing on the output when power is applied or
removed from active circuitry. The design supports nominal sample rates of 44.1/48kHz in single-speed
mode and 88.2/96kHz in double-speed mode.

Circuit Description.

The following detailed circuit description applies to channel 1 (sheet 1). The seven other channels are
similar.

D/A Converter

D/A converter U6 (AD1853) is powered on its DVDD pin by the main 5VD system power from the
backplane, and on its AVDD pin by higher-quality 5VA regulated on-board by U3. Power is decoupled by
ferrites FB5, FB13 and bypassed by C29, 30,45,71. U6 operates its serial digital audio port in I2S mode,
IDPM[1:0]=01. I2S signals I2S1/1,DAC_BICK/, and DAC_LRCK/ are provided by interface fpga U1 (sheet
4). Master clocks to the eight D/A chips are distributed from U1 in pairs, MCK12 driving U6and U7
(channels 1 and 2 respectively). The remaining four D/A logic inputs are under the control of host software,
via the U1 interface. DAC_RST/, DAMUTE, DEEMPH, and 96K_EN are applied to all eight D/A chips in
parallel. The SPI control port is not utilized; CLATCH, CCLK, and CDATA are connected to 0V.
Analog reference current for U6 is set at about 1mA by R22, filtered by C46, C47. The differential output
currents OUTL and OUTR are connected out-of-phase, as described above. The combined currents OUTL+
and OUTR- are fed to one summing node of dual op-amp U14 (OPA2134) through ferrite FB22, with their
counterparts similarly fed to the other summing node. The non-inverting inputs of U14 are biased at about
2.7V by the FILTR pin of U6, which sets the dc compliance voltage into which the D/A current sources are
designed to operate.
U14 acts as a current-to-voltage converter (I/V converter), producing a differential voltage from the
combined differential D/A currents. Each current-output pin of U6 sinks a bias of 1mA, and delivers full-
scale signal current of +/-0.75mA around that bias point (.25 to 1.75 mA). The output voltage at U14.1 is
determined by feedback resistor R92 (6.49k) balancing the net current into the summing node. The full-
scale ac signal voltage developed at U14.1 due to OUTL+ would be +/- (0.75mA*6.49k) = +/-4.9V; it
becomes +/-9.8V when the equal contribution of OUTR- is added.
A separate dc feedback scheme is used to eliminate dc bias from the outputs of U14. The feedback loop is
formed by R49, R48, Q3, Q4, R47, R51, and ancillary components. Q4 supplies bias currents into the
summing nodes through R47 and R51, while Q3 senses the sum of the outputs of U14 through R49 and
R88. The combination of Q3 and Q4 has high current gain, and Q3 requires a negligible base current
(<1uA) when the loop is nulled. R48 supplies a bias which must be offset by the currents through R49, R88,
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