Lexicon 960L Service Manual page 121

Read-Write timing
CPU CLK
MEM CLK
SA_ADDR
SA_RAS
SA_CAS
Reads:
SA_OE
Mem DQ
Writes:
SA_WE
Mem DQ
MEM CLK
SA_ADDR
ROW+BANK
SA_RAS
SA_CAS
Reads:
SA_OE
Mem DQ
Writes:
SA_WE
Mem DQ
MDCAS1=1100
Boot Flash (U12, sheet 2)
The Boot Flash is a 1 Mbit 3 Volt Flash memory organized as 64 k words by 16 bits. The chip is mounted in
a 44-pin PLCC socket. The Boot Flash is programmed prior to insertion onto the board but there is code in
the Boot Flash to perform updates to the code. The memory is not byte-writeable and must be programmed
on a half word boundary (16 bits).
ROW + BANK
MDCAS0 = 1100 0001 1111 0000 0111 1100 0001 1111
MDCAS1 = 1111 0000 0111 1100 0001 1111 0000 0111
MDCAS2 = 1111 1111 1111 1111 0000 0111 1100 0001
MDCNFG:TRP=4
Figure 3-2 Dram Single Transactions
COL COL+4
RD0 RD1
WD0 WD1
Last <-------------------------------------------------------
MDCAS0=1100 1100 1100 1100 1100 1100 1100 0111
MDCNFG:TRP=4
Figure 3-3 Dram Burst Transactions
RD DATA
WR DATA
MDCNFG:CDB2 = 0
COL+8 COL+12
RD2
RD3
WD2 WD3
MDCNFG:CDB2 = 0
Lexicon
TDL=00
TDL=00
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