Central Processor (Sheet 1) - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual

Central Processor (sheet 1)

The system central processor is a highly integrated microprocessor that incorporates a 32-bit StrongARM
RISC processor core, system support logic, multiple communication channels, an LCD controller, a
PCMCIA controller, and general-purpose I/O ports.
Processor Summary (U8, sheet 1)
The SA-1100 Microprocessor is a general-purpose, 32 bit RISC microprocessor with the following features:
16 Kbyte instruction cache
8 Kbyte write-back data cache
512 byte mini data cash that allocates data based on the MMU
4 entry read buffer and an 8 entry write buffer
Integral memory management unit ( MMU )
The logic outside the core and caches is grouped into the following three modules:
Memory and PCMCIA control module ( MPCM )
Memory interface supporting ROM, Flash, DRAM, SRAM, and PCMCIA control signals
System control module ( SCM )
Twenty-eight general purpose I/O ports (interrupt capable)
Real-time clock, watchdog, and interval times
Power management controller
Interrupt controller
Reset controller
Two on-chip oscillators for connection to 3.686 MHz and 32.768 kHz crystals
Peripheral control module ( PM )
Six-channel DMA controller
Gray/color, active/passive LCD controller
230 Kbps SDLC controller
16550 compatible UART
IrDA serial port (115 Kbps, 4 Mbps )
Synchronous serial port (UCB1100, UCB1200, SPI, TI, uWire )
Memory Map
Table 2-1 shows the memory SA-1100 memory map. The map is divided into four main partitions of 1
Gbyte each.
Base Address
0xE800 0000
0xE000 0000
0xD800 0000
0xD000 0000
0xC800 0000
0xC000 0000
0x8000 0000
0x4000 0000
0x3000 0000
0x2000 0000
7-40
SA-1100
Reserved
Zeros Bank
DRAM Bank 3
DRAM Bank 2
DRAM Bank 1
DRAM Bank 0
Internal Registers
Reserved
PCMCIA Socket 0
PCMCIA Socket 1
LARC2
Not used
Not used
Not used
DRAM bank 0
8 Mb Flash (alternate)
Optional PCMCIA Socket