Lexicon 960L Service Manual page 59

FFFFFFFF 1111 1111 1111 1111 1111 1111 1111 1111
AAAAAAAA 1010 1010 1010 1010 1010 1010 1010 1010
55555555 0101 0101 0101 0101 0101 0101 0101 0101
CCCCCCCC 1100 1100 1100 1100 1100 1100 1100 1100
33333333 0011 0011 0011 0011 0011 0011 0011 0011
99999999 1001 1001 1001 1001 1001 1001 1001 1001
66666666 0110 0110 0110 0110 0110 0110 0110 0110
When a DRAM Data Bus failure is encountered, the test will stop and loop continuously at the failed
address location. The address where the error occurred, along with the data sent, and the data
received is sent to the Debug Port.
Memory Test (DRAM Address Bus):
•
During this operation, the DRAM Address Bus is tested by first writing the current address into 25
memory locations of the DRAM using 32 bit words, then the same memory locations are read to verify
the data written in these locations is correct. During the test, DRAM address lines (BMA10-BMA21) are
tested using the addresses listed in the table below. Refer to the table below for the hex to binary
conversion of the data patterns:
M
HEX S
VALUE: B
C0000000 1100 0000 0000 0000 0000 0000 0000 0000
C0000004 1100 0000 0000 0000 0000 0000 0000 0100
C0000008 1100 0000 0000 0000 0000 0000 0000 1000
C0000010 1100 0000 0000 0000 0000 0000 0001 0000
C0000020 1100 0000 0000 0000 0000 0000 0010 0000
C0000040 1100 0000 0000 0000 0000 0000 0100 0000
C0000080 1100 0000 0000 0000 0000 0000 1000 0000
C0000100 1100 0000 0000 0000 0000 0001 0000 0000
C0000200 1100 0000 0000 0000 0000 0010 0000 0000
C0000400 1100 0000 0000 0000 0000 0100 0000 0000
C0000800 1100 0000 0000 0000 0000 1000 0000 0000
C0001000 1100 0000 0000 0000 0001 0000 0000 0000
C0002000 1100 0000 0000 0000 0010 0000 0000 0000
C0004000 1100 0000 0000 0000 0100 0000 0000 0000
C0008000 1100 0000 0000 0000 1000 0000 0000 0000
C0010000 1100 0000 0000 0001 0000 0000 0000 0000
C0020000 1100 0000 0000 0010 0000 0000 0000 0000
C0040000 1100 0000 0000 0100 0000 0000 0000 0000
C0080000 1100 0000 0000 1000 0000 0000 0000 0000
C0100000 1100 0000 0001 0000 0000 0000 0000 0000
C0200000 1100 0000 0010 0000 0000 0000 0000 0000
C0400000 1100 0000 0100 0000 0000 0000 0000 0000
C0800000 1100 0000 1000 0000 0000 0000 0000 0000
C1000000 1100 0001 0000 0000 0000 0000 0000 0000
C2000000 1100 0010 0000 0000 0000 0000 0000 0000
When a DRAM Address Bus failure is encountered, the test will stop and loop continuously at the failed
address location. The address where the error occurred, along with the data sent, and the data
received is sent to the Debug Port.
NOTE: Since this test utilizes 32 bit words (4 bytes) it is not possible to test the address lines 0 & 1.
Copy ROM to RAM:
•
BINARY CONVERSION:
L
S
B
Lexicon
6-27