Signal Polarity; System Interface Logic; Control Interface; Register Descriptions - Lexicon 960L Service Manual

Relays for each pair of channels are energized by one transistor when software sets RLY_MUTE/ to a high
logic level.

Signal Polarity

A positive digital value entering interface U1 from the backplane is converted to the corresponding positive
value in the right channel of the D/A I2S stream, and its binary complement in the left channel. This makes
U14.1 positive (U14.7 negative), U22.7 (CH1) negative, and U26.3 (J2.2) positive, so a positive digital input
value from the backplane produces a positive voltage on the conventional differential XLR output.

System Interface Logic

FPGA U1 (Xilinx XCS05, sheet 5) is the interface between the I/O backplane control, data (host and audio),
and clock buses and the D/A converters and their associated controls. When power is applied to the card,
the FPGA automatically receives its internal configuration from companion SROM U2. Configuration takes a
few tens of msec, after which the onboard logic assumes its default state and is ready to be
interrogated/programmed by system software.

Control Interface

The Analog Output card appears as two, byte-wide ports on the I/O backplane databus IOBUS_DATA[7:0],
at the addresses determined by the decoding of SLOT_SEL/ and one address bit, IOBUS_ADDR[0].
IOBUS_WR/RD determines the direction of data transfer (low=write, high=read), with IOBUS_DS/ being
asserted low during data transfers. U1 captures write data on the rising edge of IOBUS_DS/. Five pins of
the fpga are control outputs whose states get programmed from the host computer. Four pins, DEEMPH,
DAMUTE, DCA_RST/, 96K_EN, control all the D/A converters in parallel and the fifth, RLY_MUTE/,
controls the mute relays, as already described. IOBUS_RESET/ and PWROK are not used. When low,
ALL_MUTE/ forces zeroes on all I2S data lines, I2S0-7.

Register Descriptions

ADDR NAME Access Default
0x00 IDREG(7:0) RO
IDREG(7:4) RO
IDREG(3:0) RO
0x01 CTLREG(7:0)
CTLREG(7) RW
CTLREG(6:5) RW
CTLREG(4) RW
CTLREG(3) RW
CTLREG(2) RW
CTLREG(1) RW
CTLREG(0) RW

Clock Interface

The following onboard digital audio clocks are derived from bus clocks TMIX_CKI and TMIX_WCKI:
I2S_FS/, I2S_64FS/, and I2S_256FS The bus clocks TMIX_CKI/2, IOBUS_WCLK/, IOBUS_64FS/, and
IOBUS_256FS are not used. Ancillary clocks for charge pumps are also derived from TMIX_CKI:
VBOSCU/, VBOSCD, and VCCOSC (see below). I2S_FS/ and I2S_64FS/ scale with sample rate FS.
Description
Value
0x21 Board ID register
2 Type(2=AOUT)
1 PCB Revision number
NA Reserved.
0X3 Octal Select : selects which IOBUS octal pairs are rec'd by the AOUT FPGA
00 AOUT octals rec'd from TMIX2_SERD0/TMIX2_SERD1
01 AOUT octals rec'd from TMIX2_SERD8/TMIX2_SERD9
10 AOUT octals rec'd from TMIX2_SERD10/TMIX2_SERD11
11 AOUT input octals set to zero
0 DEEMPHASIS. Active High. When asserted, hardware de-emphasis is enabled.
0 RELAY_MUTE/. Active Low. When asserted. All D/A output relays are in the
mute state
0 DAC_RESET/. Active Low. When asserted, all DACs are in reset state.
Software must assert, then negate CTLREG(2) to complete a soft reset
sequence.
0 DAMUTE. Active High. When asserted, DAMUTE enables the built in D/A soft
mute
capability. Refer to the AD1853 spec for details.
0 96K_EN. Active high. When asserted, D/A's operate in double speed
mode(88.2 or 96K)
Lexicon
7-23