Lexicon 960L Service Manual page 97

13 TMIX_CKI
78 TMIX_CKI/2
51 TMIX_WCKI
7 IOBUS_WCLK/
35 IOBUS_64FS/
10 IOBUS_128FS
57 IOBUS_256FS
8 I2S_FS/
37 I2S_64FS/
9 I2S_256FS
Pin Name
Serial Audio
3 I2S0
4 I2S1
5 I2S2
6 I2S3
19 SDO0
18 SDO1
14 SDO2
20 SDO3
24 SDO4
25 SDO5
Audio Control
27 CONV_RESET/
26,28 DFS1,DFS0
FPGA Support
32 MODE
55 PROG/
73 CCLK
53 DONE
41 INIT/
71 DIN
15,16, TDI,TCK,TMS
17
75 TDO
INPUT TMIX_CKI - master TMIX clock. All local clocks(I2S_FS/, I2S_64FS/,
I2S_256FS) are derived from this clock and TMIX_WCKI. Input frequency
is nominally 24.576Mhz or 22.5792Mhz for 48/96Khz and 44.1/88.2
sample rates respectively.
INPUT TMIX_CKI/2 - not used
INPUT TMIX_WCKI - TMIX word clock. Rising edge denotes start of octal frame.
Input frequency is 44.1Khz or 48Khz.
INPUT Not used
INPUT Not used
INPUT Not used
INPUT Not used
OUTPUT AD Frame Sync - falling edge denotes start of frame. Locally generated.
OUTPUT AD bit clock - falling edge denotes start of bit period. Locally generated.
OUTPUT AD MCLK signal. Locally generated.
Description
Type
INPUT I2S audio data for channels 1-2
INPUT I2S audio data for channels 3-4
INPUT I2S audio data for channels 5-6
INPUT I2S audio data for channels 7-8
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 0. Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 1.Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 2.Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 3.Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 10.Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT, TMIX Octal data. Drives TMIX1 Octal 11.Tristate control is determined by
TRISTATE the octal select field in the AIN control register(see register description for
details)
OUTPUT CONVERTER RESET. 0 : resets AD conveters, 1 : normal operation
OUTPUT DFS1-0 : determines AD sample rate(1x vs 2x). (See AIN control register
description for details)
INPUT MODE - Serial download interface mode signal. Nomimally zero for
loading from external SPROM
INPUT FPGA Program. 0 : causes the FPGA to reload its program from the
external SPROM.
OUTPUT CCLK . Serial PROM clock signal
OUTPUT FPGA DONE - Asserted when FPGA program cycle has completed.
OUTPUT FPGA serial download initialization signal.
INPUT FPGA configuration data from SPROM
INPUT JTAG Interface. Not used
OUTPUT JTAG Interface. Not used
Lexicon
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