Larc2 Interface; Cpld Logic - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual
connected, both resistors get disconnected and the input becomes a bridging, high-impedance loop,
allowing the line to be chained to other equipment and terminated elsewhere in the system.
The input squarewave is applied to the high-impedance non-inverting input of line receiver U13
(75ALS180), that produces the buffered waveform BNC_WCIN. The receiver threshold is set at about 1.6V
by resistors R25 and R26. BNC_WCIN is fed to a multiplexer implemented within the programmed logic of
CPLD U2 (XC9572), where it can be selected by software to be the reference for the on-board PLL.
A squarewave derived from the internal wordclock, BNC_WCOUT, is generated by U2 and fed to the line
driver section of U13. OUTPUT BNC J8 is driven by the non-inverting output of U13. Output impedance is
around 15 ohms, and output voltage is typically 3.5Vpeak when loaded with 75 ohms to ground.

Larc2 Interface

J9 and J10, female 9-pin D-subminiature connectors, are ports for LARC2 remote control consoles,
REMOTE 1 and 2. Each port delivers fused 12Vdc power and provides separate full-duplex RS-422 serial
communication channels.
J9.5 delivers 12Vdc from the system 12V supply through self-resetting fuse PS1 (0.75Amp). Normally, the
fuse exhibits a low series resistance, a few tenths of an ohm. When overloaded by currents >1.5Amp, the
fuse undergoes self-heating and switches to a high resistance state due to the thermal characteristics of its
material. This high resistance limits the current drawn from the supply under the overload condition. The
fuse maintains the high-resistance state as long as it dissipates about 0.8W, or about 66mA at 12V, which
is the short-circuit condition. The trip time is typically 0.2 seconds at 8 Amps, which is a severe overload.
Smaller overloads can take many seconds to trip. Resetting occurs when the load is removed and the fuse
cools, returning to the low-resistance state.
Full-duplex remote serial communication is based on RS-232 COM ports built into the NLX motherboard.
U14 (75ALS180) forms the interface between the bipolar unbalanced RS-232 levels of the COM1 port and
the unipolar balanced RS-422 levels of the REMOTE 1 port. The RS-232 signals from COM1 connect to the
IO backplane J6 via a ribbon cable connected to the 9-pin D-sub connector on the IO panel of the
motherboard. The backplane brings COM1 signals to J1 as RS232_TXD1/ and RS232_RXD1/
(marking=negative, spacing=positive). RS232_TXD1/ feeds the driver section of U14 through R27 and dual
diode D9 (BAV99), which essentially limits the bipolar RS232 signal to a logic level TXD1/ within the range
acceptable by U14. When the serial port is idle (i.e. marking), TXD1/ is low. The output of the U14 driver is
wired to make TX1+ high and TX1- low, so the marking state of the differential RS422 signal is positive,
according to convention. (The U14 driver is wired as an inverting stage because of the sense of
RS232_TXD1/).
The receiver section of U14 accepts differential RS422 input from REMOTE 1 and produces logic-level
signal RS232_RXD1/. As with the driver, the receiver is wired as an inverting stage, such that when the
difference between RX1+ and RX1- is positive (i.e. marking), RS232_RXD1/ is low, in accordance with
RS232 conventions. With no external connection to J9, R28 and R29 bias the differential pair in the marking
(positive) state, overriding the default biasing of the receiver input. The RS232_RXD1/ logic level is fed
directly to the COM1 RS232 line receiver on the motherboard. Although the line receiver normally expects
wide-range bipolar RS232 levels, its input threshold is essentially TTL, and it operates properly when driven
locally with conventional unipolar logic levels.
Similarly, REMOTE 2 communication is based on the COM2 RS232 port on the NLX motherboard. COM2
is implemented as a 10-pin header on the NLX motherboard, connected by ribbon cable to IO backplane
J7.

CPLD Logic

U2 (Xilinx XC9572, sheet 2) is a Complex Programmable Logic Device, which is custom-programmed to
perform several different functions. Unlike the FPGAs on other modules, the internal logic of the CPLD is
permanently programmed, so no configuration needs to be loaded each time power is applied. The CPLD
7-8