Lexicon 960L Service Manual page 91

Lexicon
PLL Action
PLL action can be understood by first disregarding the effect of R10 and D2 in the active filter. In a perfect
lock condition, neither the UP/ or DOWN logic level is asserted, so there is ideally no summing-node current
because D3 and D4 are both reverse-biased, and therefore the voltage out of integrator U6 holds at some
constant value. The VCO output is correspondingly constant, and its frequency and phase are exactly the
constant value required to satisfy the PFD lock condition. In lock, there are no error signals to integrate. The
correct control voltage exists and remains constant, at a value that was attained by integrating errors that
occurred previously.
If the PFD generates UP/ pulses, either because frequency is too low or because phase is lagging, the
integrator output voltage rises in increments that depend on the width of the UP/ pulses. When UP/ is low,
D3 is forward biased and current flows through R9, charging the integrator capacitors. As the voltage rises,
so does the frequency, and eventually the feedback action of the loop reduces the low-frequency/lagging-
phase error to zero. The loop is satisfied and no further phase error occurs, so no further change to the
VCO output occurs, which is the locked condition described above. A similar description applies to
approach from the opposite direction. The magnitude of the up and down current pulses is nominally the
same due to the 2.5V bias at the non-inverting input of U6.
If the VCO voltage at the cathode of D7 drops below 1.7V, the varactor begins to forward bias, and the
VCO may completely cease to oscillate. D2 in the feedback path of U6 limits the VCO voltage to a low
value of about 1.8V to ensure that the VCO always oscillates. At normal VCO operating voltages, D2 is
reverse-biased and has negligible effect.
Jitter
To a degree, a PLL locks to the average of the reference frequency, rejecting short-term variations in
phase, or jitter. The ability of the loop to track or reject variations in the reference phase is characterized by
its jitter gain as a function of jitter frequency. This PLL is a second-order system. Its jitter gain is slightly
overdamped due to R12, with a corner frequency around 150Hz principally determined by C20 in
conjunction with the dc gain around the loop.
The jitter gain of the PLL and the intrinsic jitter of the VCO both exceed the requirement of AES3-1992
Amendment-1-1997.
Phase Detector Offset
As a practical matter, it is undesirable to operate the PFD at zero phase error. Because finite response
times are involved in the logic that generates the UP/ and DOWN error signals, the PFD has a zone around
zero-phase where it is non-linear, which causes undesirable loop operation. Improved loop performance is
achieved by intentionally introducing a small dc error in the integrator, by means of R10. A small current
from the summing node to ground through R10 acts to raise the output voltage and VCO frequency. To
maintain lock, the loop compensates for this by developing a narrow positive DOWN pulse whose integral
over one period is equal and opposite to the effect of R10, such that there is no net dc into the summing
node. R10 is chosen to require a compensating DOWN duty cycle of about 1/128, and this small phase
error in the PFD keeps it away from the zero-phase point. In lock, then, the PLL wordclock applied to the
PFD is made to lead the reference wordclock by a constant phase offset, 1/128 of the wordclock period, so
the PLL wordclock is not aligned with the reference. Within the CPLD, an additional wordclock is produced
that is delayed (lags) by precisely this amount. It is this wordclock, which is almost perfectly aligned with the
reference that is distributed for use throughout the 960L. The PLL wordclock that actually feeds the PFD
has no visibility outside the CPLD.
Lock Detector
If the clocks from the PLL are not closely aligned with the reference, the PLL is considered to be unlocked.
If lock is not within plus or minus 1/128 of a wordclock period on any clock cycle, logic within the CPLD
generates a LKERRDET pulse, which triggers integrating one-shot U5. R6 and C8 set the timing of U5 at
about 50 msec. The output of U5 is returned to the CPLD where it can be polled by software to ensure the
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