External Pll; Expansion Interface - Analog Devices Lite ADSP-21375 EZ-KIT System Manual

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External PLL

The ADSP-21375 EZ-KIT Lite contains an external phase lock loop to
help generate a faster and more stable master input clock,
uses DAI pin 3 as an input clock from the ADSP-21375 processor. The
new clock generated by PLL connects to the processor via DAI pin 2.
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate how to configure and use the board's external PLL.

Expansion Interface

The expansion interface consists of three 90-pin connectors.
shows the interfaces each connector provides. For the exact pinout of the
connectors, refer to "ADSP-21375 EZ-KIT Lite Schematic" on page
The mechanical dimensions of the connectors can be obtained from
Technical Support.
Table 2-2. Expansion Interface Connectors
Connector Interfaces
5V,
J1 ADDR23–0
3.3V,
J2 FLAG3–0
5V, 3.3V, reset, parallel port control signals
J3
Limits to current and interface speed must be taken into consideration
when using the expansion interface. The maximum current limit is depen-
dent on the capabilities of the used regulator. Additional circuitry also can
add extra loading to signals, decreasing their maximum effective speed.

Analog Devices does not support and is not responsible for the
effects of additional circuitry.
ADSP-21375 EZ-KIT Lite Evaluation System Manual
ADSP-21375 EZ-KIT Lite Hardware Reference
,
DATA31–0
, , , SDRAM control signals
DAIP20–1 DPI14–1
. The PLL
MCLK
Table 2-2
B-1.
2-7