ST STM32L1 Series Application Note page 41

AN4612
Table 19. FLASH differences between STM32L1 Series and STM32L4 Series (continued)
FLASH
0x1FF8 0000 - 0x1FF8001F (all Cat.x)
Option Bytes
0x1FF8 0080 - 0x1FF8 009F (Cat.4,5)
0x4002 3C00 - 0x4002 3FFF
Flash memory
interface
Program memory: Mass/Page (256 bytes)
Erase
DATA EEPROM memory: byte/ halfword/ word /
granularity
double word
Read protection
(RDP)
Proprietary
code readout Granularity: 1 sector (4 Kbyte)
protection
(PCROP)
Write protection
Granularity: 1 sector (4 Kbyte)
(WRP)
nRST_STOP
nRST_STDBY
IWDG_SW
BOR_LEV[3:0]
User Option
bytes
nBFB2
Color key:
= New feature or new architecture (difference between STM32L1 and STM32L4 Series)
= Same feature, but specification change or enhancement
= Feature not available (NA)
= Difference between STM32L1 and STM32L4 Series highlight
STM32L1 Series
-
Level 0 no protection
RDP = 0xAA
Level 1 memory protection
RDP ≠ (Level 2 & Level 0)
Level 2 RDP = 0xCC
NA
NA
NA
NA
NA
NA
NA
DocID027094 Rev 3
STM32L4 Series
0x1FFF 7800 - 0x1FFF 780F (bank1)
0x1FFF F800 - 0x1FFF F80F (bank2)
(only bank1 for Cat. 4 devices)
0x4002 2000 - 0x4002 23FF
Different from STM32L1 Series
Page erase (2Kbytes), Bank erase and Mass
erase (all banks)
(1)
1 PCROP area per bank
Granularity: 64-bit
PCROP_RDP option: PCROP area preserved
when RDP level decreased.
2 write protection areas per bank
Granularity: 2 Kbyte
nRST_STOP
nRST_STDBY
IWDG_SW
IWDG_STOP, IWDG_STDBY
WWDG_SW
BOR_LEV[2:0]
BFB2 (except for Cat. 4 devices)
nBOOT1
SRAM2_RST, SRAM2_PE
DUAL BANK (except for Cat. 4 devices)
nBOOT0 (only for Cat. 4 devices)
nSWBOOT0 (only for Cat. 4 devices)
Peripheral migration
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