ST STM32L1 Series Application Note page 35

AN4612
Table 15. PWR differences between STM32L1 Series and STM32L4 Series (continued)
PWR
Battery
backup
domain
Brownout reset (BOR)
BOR can be disabled after power-on
Power supply
supervisor
Sleep mode
Low-power run mode (up to 128 kHz)
Low-power sleep mode (up to 128 kHz)
Stop mode
Low-power
modes
Standby mode (V
STM32L1 Series
NA
Integrated POR / PDR circuitry
Programmable voltage detector (PVD)
NA
domain powered off)
CORE
NA
DocID027094 Rev 3
Peripheral migration
STM32L4 Series
– RTC with backup registers (128 bytes)
– LSE
– PC13 to PC15 I/Os
– 3 tamper pins
Brownout reset (BOR)
BOR is always enabled, except in
Shutdown mode
4 peripheral voltage monitoring (PVM)
– PVM1 for V
DDUSB
– PVM2 for V (for Cat. 2 devices
DDIO2
only)
– PVM3/PVM4 for V
DDA
Sleep mode
Low-power run mode (up to 2 MHz)
Low-power sleep mode (up to 2 MHz)
System clock is limited to 2 MHz, but I2C
and U(S)ART/LPUART can be clocked
with HSI16 at 16 MHz.
Stop 0, Stop 1 and Stop 2 mode
Some additional functional peripherals (cf
wakeup source)
Standby mode (V domain powered
CORE
off) with new features:
– BOR is always ON
– SRAM2 content can be preserved
– Pull-up or pull-down can be applied on
each I/O
Shutdown mode (V
CORE
off and power monitoring off)
(~1.65 V/ ~2.2 V)
domain powered
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