ST STM32L1 Series Application Note page 25

AN4612
Peripheral
I2C2
SDIO
SDMMC
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
AES
Color key:
= Differences between STM32L1 and STM32L4 Series
1. For High-density value line devices, the DAC DMA requests are mapped respectively on DMA1 Channel 3
and DMA1 Channel 4.
2. Not applicable on STM32L4 Cat. 4 device
Table 10. DMA request differences migrating STM32L1 Series
to STM32L4 Series (continued)
DMA request
I2C2_Rx
I2C2_Tx
SDIO
SDMMC
TIM2_UP
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
TIM3_UP
TIM3_CH1
TIM3_TRIG
TIM3_CH3
TIM3_CH4
TIM4_UP
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM5_UP
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM5_CH4
TIM5_TRIG
TIM5_COM
TIM6_UP
TIM7_UP
AES_OUT
AES_IN
DocID027094 Rev 3
STM32L1 Series
DMA1_Channel5
DMA1_Channel4
DMA2_Channel4
NA
DMA1_Channel2
DMA1_Channel5
DMA1_Channel7
DMA1_Channel1
DMA1_Channel7
DMA1_Channel3
DMA1_Channel6
DMA1_Channel6
DMA1_Channel2
DMA1_Channel3
DMA1_Channel7
DMA1_Channel1
DMA1_Channel4
DMA1_Channel5
DMA2_Channel2
DMA2_Channel5
DMA2_Channel4
DMA2_Channel2
DMA2_Channel1
DMA2_Channel1
DMA2_Channel1
DMA1_Channel2
DMA1_Channel3
DMA2_Channel3
DMA2_Channel5
Peripheral migration
STM32L4 Series
DMA1_Channel5
DMA1_Channel4
NA
DMA2_Channel4
DMA2_Channel5
DMA1_Channel2
DMA1_Channel5
DMA1_Channel7
DMA1_Channel1
DMA1_Channel7
(2)
DMA1_Channel3
(2)
DMA1_Channel6
(2)
DMA1_Channel6
(2)
DMA1_Channel2
(2)
DMA1_Channel3
(2)
DMA1_Channel7
(2)
DMA1_Channel1
(2)
DMA1_Channel4
(2)
DMA1_Channel5
(2)
DMA2_Channel2
(2)
DMA2_Channel5
(2)
DMA2_Channel4
(2)
DMA2_Channel2
(2)
DMA2_Channel1
(2)
DMA2_Channel1
(2)
DMA2_Channel1
DMA1_Channel3
DMA2_Channel4
DMA1_Channel4
DMA2_Channel5
DMA2_Channel3
DMA2_Channel2
DMA2_Channel5
DMA2_Channel1
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