ST STM32L1 Series Application Note page 33

AN4612
In STM32L4 Series: The RTC and LCD Glass clock is derived from one of the three
following sources: LSE, LSI, HSE divided by 32 (PCLK frequency should always be
greater than or equal to RTC Clock frequency).
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ADC:
In STM32L1 Series, the ADC features two clock schemes:
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In STM32L4 Series, the input clock of the ADCs can be selected between two different
clock sources:
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Refer to the STM32L1 and STM32L4 Series reference manuals for more details.
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DAC:
In STM32L4 Series, in addition to the PCLK1 clock, LSI clock is used for the sample
and hold operation.
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U(S)ARTs:
In STM32L1 Series, the U(S)ART clock is APB1 or APB2 clock (depending on which
APB bus the U(S)ART) is mapped to.
In STM32L4 Series, the U(S)ART clock is derived from one of the four following
sources: system clock (SYSCLK), HSI16, LSE, APB1 or APB2 clock (depending on
which APB bus the U(S)ART is mapped to).
Using a source clock independent from the system clock (ex: HSI16) allows to change
the system clock on the fly without need to reconfigure U(S)ART peripheral baud rate
prescalers.
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I2Cs:
In STM32L1 Series, the I2C clock is APB1 clock (PCLK1).
In STM32L4 Series, the I2C clock is derived from one of the three following sources:
system clock (SYSCLK), HSI16, APB1 (PCLK1).
Using a source clock independent from the system clock (ex: HSI16) allows to change
the system clock on the fly without need to reconfigure I2C peripheral timing register.
Clock for the analog circuitry: ADCCLK. This clock is always the HSI oscillator
clock. A divider by 1, 2 or 4 allows to adapt the clock frequency to the device
operating conditions. This configuration is done using ADC_CCR[ADCPRE] bits.
The ADC clock depends also on the voltage range V CORE . When product voltage
range 3 is selected (V CORE = 1.2 V), the ADC is low speed (ADCCLK = 4 MHz,
250 Ksps).
Clock for the digital interface (used for register read/write access). This clock is the
APB2 clock. The digital interface clock can be enabled/disabled through the
RCC_APB2ENR register (ADC1EN bit) and there is a bit to reset the ADC through
RCC_APB2RSTR[ADCRST] bit.
The ADCs clock can be derived (selected by software) from one of the three
following sources: system clock (SYSCLK), PLLSAI1 VCO (PLLADC1CLK),
PLLSAI2 VCO (PLLADC2CLK) (only on Cat. 2 devices). In this mode, a
programmable divider factor can be selected (1, 2, ..., 256 according to bits
PREC[3:0]).
The ADC clock can be derived from the AHB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider
factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]).
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Peripheral migration
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