Supermicro SuperStorage SSG-6029P-E1CR24H User Manual page 45

SuperStorage SSG-6029P-E1CR24H/L User's Manual
Note: Please refer to the drawing on the next page for the locations of DIMM modules.
P1- P1-
Modes
DIMMF1 DIMMF2
AD DRAM1 DCPMM
MM DRAM1 DCPMM
AD + MM DRAM3 DCPMM
AD DRAM1 -
MM DRAM2 -
AD + MM DRAM3 -
AD DRAM1 -
MM DRAM1 -
AD + MM DRAM3 -
AD DCPMM -
MM DCPMM -
AD + MM DCPMM -
AD DCPMM -
P1- P1-
Modes
DIMMF1 DIMMF2 DIMME1
AD DRAM1 - DRAM1
AD* DRAM1 - DRAM1
DDR4 Type
DRAM1
DRAM2
DRAM3
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
Capacity
DCPMM
•
* 2nd socket has no DCPMM DIMM
•
For MM, general NM/FM ratio is between 1:4 and 1:16. Excessive capacity for FM can be used for AD. (NM = Near
Memory; FM = Far Memory)
•
For each individual population, rearrangements between channels are allowed as long as the resulting population is
compliant with the PDG rules for the 82xx/62xx/52xx/42xx platform.
•
For each individual population, please use the same DDR4 DIMM in all slots.
•
For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM
per node case. Currently, DCPMM modules operate at 2666 MHz.
•
No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
•
This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.
Symmetric Population within 1 CPU Socket
P1- P1- P1- P1-
DIMME1 DIMME2 DIMMD1 DIMMD2
DRAM1 DCPMM DRAM1 DCPMM
DRAM1 DCPMM DRAM1 DCPMM
DRAM3 DCPMM DRAM3 DCPMM
DRAM1 - DRAM1 DCPMM
DRAM2 - DRAM2 DCPMM
DRAM3 - DRAM3 DCPMM
DRAM1 DCPMM DRAM1 DCPMM
DRAM1 DCPMM DRAM1 DCPMM
DRAM3 DCPMM DRAM3 DCPMM
DRAM1 - DRAM1 -
DRAM1 - DRAM1 -
DRAM3 - DRAM3 -
DRAM1 DRAM1 DRAM1 DRAM1
Asymmetric Population within 1 CPU Socket
P1- P1- P1- P1-
DIMME2 DIMMD1 DIMMD2
- DRAM1 -
- DRAM1 -
Legend (for the two tables above)
RDIMM 3DS RDIMM LRDIMM
RDIMM -
RDIMM 3DS RDIMM LRDIMM
Legend (-for the two tables above)
Any Capacity (Uniformly for all channels for a given configuration)
P1- P1- P1-
DIMMA2 DIMMA1 DIMMB2 DIMMB1
DCPMM DRAM1 DCPMM DRAM1
DCPMM DRAM1 DCPMM DRAM1
DCPMM DRAM3 DCPMM DRAM3
DCPMM DRAM1 - DRAM1
DCPMM DRAM2 - DRAM2
DCPMM DRAM3 - DRAM3
DCPMM DRAM1 DCPMM DRAM1
DCPMM DRAM1 DCPMM DRAM1
DCPMM DRAM3 DCPMM DRAM3
- DRAM1 - DRAM1
- DRAM1 - DRAM1
- DRAM3 - DRAM3
DRAM1 DRAM1 DRAM1 DRAM1
P1- P1- P1- P1-
DIMMA2 DIMMA1 DIMMB2 DIMMB1
DCPMM DRAM1 - DRAM1
DCPMM DRAM1 - DRAM1
Capacity
3DS LRDIMM Any Capacity
-
Refer to Validation Matrix (DDR4 DIMMs
validated with DCPMM) below.
-
45
P1- P1- P1- Channel
DIMMC2 DIMMC1 Config.
DCPMM DRAM1 2-2-2
DCPMM DRAM1 2-2-2
DCPMM DRAM3 2-2-2
- DRAM1 2-1-1
- DRAM2 2-1-1
- DRAM3 2-1-1
- DRAM1 2-2-1
- DRAM1 2-2-1
- DRAM3 2-2-1
- DCPMM 1-1-1
- DCPMM 1-1-1
- DCPMM 1-1-1
- DCPMM 2-2-1
P1- P1- Channel
DIMMC2 DIMMC1 Config.
- DRAM1 2/1-1-1
- DRAM1 2/1-1-1