Interrupt Controller Programming Model; Interrupt Source Register (Intsrc; Normal Interrupt Enable Register (Nier; Interrupt Source Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

C.2 Interrupt Controller Programming Model
Control and status registers for the interrupt controller begin at address 0x40002000.
Address
10000000
10000004
10000008
1000000C
10000010
C.2.1 Interrupt Source Register (INTSRC)
Access the 32-bit interrupt source register with 32-bit loads only.
INTSRC — Interrupt Source Register
31 30 29 28
IN31 IN30 IN29 IN28
RESET:
15 14 13 12
IN15 IN14 IN13 IN12
RESET:
INx — Interrupt Source x
This bit indicates the state of the corresponding interrupt source.
0 = Negated
1 = Asserted
Bits [0:2] of this register are tied to logic level one to allow software to schedule inter-
rupts by enabling one or more of these "sources" in the appropriate interrupt enable
register(s) (NIER, FIER).
C.2.2 Normal Interrupt Enable Register (NIER)
Access the 32-bit normal interrupt enable register with 32-bit loads and stores only.
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C-2
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Table C-2 Interrupt Controller Address Map
Use

Interrupt Source Register (INTSRC)

Normal Interrupt Enable Register (NIER)

Fast Interrupt Enable Register (FIER)
Normal Interrupt Pending Register (NIPND)
Fast Interrupt Pending Register (FIPND)
27 26 25 24
IN27 IN26 IN25 IN24
11 10 9 8
IN11 IN10 IN9 IN8
Figure C-1 Interrupt Source Register
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Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
Supervisor Only
23 22 21 20
IN23 IN22 IN21 IN20
7 6 5 4
IN7 IN6 IN5 IN4
Access
10000000
19 18 17 16
IN19 IN18 IN17 IN16
3 2 1 0
IN3 1 1 1
MMC2001
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