Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual page 133

DOZE — Doze Mode
When the CPU executes a doze instruction and the system is placed in the doze
mode, the DOZE bit affects operation of the ISPI. When this bit is set, the ISPI is dis-
abled in doze mode. Refer to the description in 12.6 ISPI Operation in Low-Power
System Modes.
0 = ISPI unaffected in doze mode
1 = ISPI disabled in doze mode
At reset, this bit is cleared to zero.
SPI_EN — ISPI Enable
In either master mode, this bit controls the value of the SPI_EN pin. The sense of the
SPI_EN pin is determined by the SNS bit. In interval mode, the SPI_EN pin is
asserted only when XCH is active. The SPI_EN bit must be programmed to a one for
any master mode transfer to occur. In slave mode, the ISPI state machine uses the
input value on the SPI_EN pin, and this register bit is ignored. Further, the SPI_EN
register bit will not reflect the value of the SPI_EN pin in slave mode.
0 = Negated
1 = Asserted
SNS — SPI_EN Sense
The SNS bit controls the sense of the SPI_EN pin relative to the SPI_EN register bit
in the ISPI control register. This is required because in interval mode, the state
machine must assert and then negate the SPI_EN pin. The SNS bit has an effect only
when the SPI_EN pin is an output. If the SPI_EN pin is an input, then it is active low,
and the SNS bit has no effect.
0 = SPI_EN pin is active low
1 = SPI_EN pin is active high
DRV — Drive Type
This bit controls the configuration of the SPI_CLK, SPI_EN and SPI_MOSI output
buffers in either master mode of the ISPI (MSTR=1). In slave mode, this bit is ignored.
0 = Outputs are totem-pole in either master mode
1 = Outputs are open-drain in either master mode
MSTR — Master Mode
This bit controls the mode of the ISPI. In slave mode, the SPI_CLK and SPI_EN pins
are inputs; in the master modes, they are outputs.
0 = ISPI operates in slave mode
1 = ISPI operates in either interval mode or manual mode (see IVL_EN in SICR)
IRQ_EN — Interrupt Request Enable
This bit enables/disables the ISPI interrupt request output signal. This bit is cleared to
zero on reset.
0 = Interrupts disabled
1 = Interrupts enabled
MOTOROLA
12-6
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INTERVAL MODE SERIAL PERIPHERAL INTERFACE
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MMC2001
REFERENCE MANUAL