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RXD Pin
1
1 1
1
1
Samples
[1]
[2]
RT CLK
(16X Bit
Rate)
RT CLK
State
Reset RT
Figure 11-12 shows the details of the ideal case of start-bit recognition. All samples
taken at [1] detect logic ones on the RXD line and correspond to the idle-line time or a
stop-bit time prior to this start bit. At [2] a logic zero sample is preceded by four logic
one samples. These five samples are the start-bit qualifiers. The beginning of the
start bit time is tentatively perceived to occur between the fourth logic one sample
and the logic zero sample of the start qualifiers. Next, the samples at RT2, RT3, RT4,
RT5, RT6, and RT7 [3] are taken to verify that this bit time is indeed the start bit. The
samples at RT8, RT9, and RT10 (or RT9, RT10, and RT11) are called the data sam-
ples [4]. These samples drive a majority voting circuit to determine the logic sense of
the bit time.
In this ideal case, the actual start bit and the perceived start bit match. The resolution
of the RT clock leads to an uncertainty about the exact placement of the leading edge
of the start bit. The uncertainty in the placement of the edge will be one-sixteenth of a
bit-time.
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Perceived Start Bit
Actual Start Bit
0
0
0
0
0
0 0
0
[3]
Figure 11-12 Start Bit — Ideal Case
For More Information On This Product,
Go to: www.freescale.com
0
0
[4]
LSB
MOTOROLA
11-19
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