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16.8.2 Breakpoint Address Base Registers (BABA, BABB)
The 32-bit breakpoint address base registers (BABA, BABB) store memory break-
point base addresses. BABA and BABB can be read or written through the OnCE
serial interface. Before enabling breakpoints, the external command controller should
load these registers.
16.8.3 Breakpoint Address Mask Registers (BAMA, BAMB)
The 32-bit breakpoint address mask registers (BAMA, BAMB) store memory break-
point base address masks. BAMA and BAMB can be read or written through the
OnCE serial interface. Before enabling breakpoints, the external command controller
should load these registers.
16.8.4 Breakpoint Address Comparators
The breakpoint address comparators are not externally accessable. Each compares
the memory address stored in MAL with the contents of BABx, as masked by BAMx,
and signals the control logic when a match occurs.
16.8.5 Memory Breakpoint Counters (MBCA, MBCB)
The 16-bit memory breakpoint counter x (MBCx) register is loaded with a value equal
to the number of times, minus one, that a memory access event should occur before
a memory breakpoint is declared. The memory access event is specified by the RCx
and BCx[4:0] bits in the OCR register and by the memory base and mask registers.
On each occurrence of the memory access event, the breakpoint counter, if currently
non-zero, is decremented. When the counter has reached the value of zero and a
new occurrence takes place, the ISBKPTx signal is asserted and causes the CPU's
BRKRQ input to be asserted. The MBCx can be read or written through the OnCE
serial interface.
Anytime the breakpoint registers are changed, or a different breakpoint event is
selected in the OCR, the breakpoint counter must be written afterward. This assures
that the OnCE breakpoint logic is reset and that no previous events will affect the new
breakpoint event selected.
16.9 OnCE Trace Logic
The OnCE trace logic allows the user to execute instructions in single or multiple
steps before the device returns to debug mode and awaits OnCE commands from the
debug serial port. (The OnCE trace logic is independent of the M•CORE trace facility,
which is controlled through the trace mode bits in the M•CORE processor status reg-
ister). The OnCE trace logic block diagram is shown in Figure 16-8.
MOTOROLA
16-14
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Freescale Semiconductor, Inc.
OnCE™ DEBUG MODULE
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MMC2001
REFERENCE MANUAL
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