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RXD Pin
Samples
1
1 1
1
1
[1]
RT CLK
(16X Bit
Rate)
RT CLK
State
Reset RT
The case depicted in Figure 11-16 is similar to the previous case. In this case the
start bit is not detected. The frame will be lost or in error, depending on the data in the
actual frame and when the start logic got synchronized. In this case, [1] qualifies the
start edge. However, the samples in [2] are not all logic zero due to the presence of
noise which causes the sample RT7 to be erroneously read as logic one. Thus, the
tentative start edge is rejected and the search for the start edge qualifier is started
once again. This happens even though all the data samples in the start bit [3] were
logic zero. If this were anything but a start bit, the voting logic would have taken the
right decision.
11.7 UART Operation in Low-Power System Modes
The UART serial interface operates as long as the 16x bit clock generator is provided
with the system clock. The peripheral interface is operational while the CPU_CLK is
running. The three bits RXEN, TXEN and UART EN, set by the user, give the capabil-
ity to control low-power modes through software. Table 11-5 shows UART functional-
ity while in hardware controlled low-power modes.
Table 11-5 UART Low-Power Mode Operation
System Clock
UART Serial Interface
Module Interface
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
No Start Bit Found
Actual Start Bit
0
0
0
0
0
0 1
0
[2]
Figure 11-16 Start Bit — Noise Case Four
Normal Mode
Wait Mode
On
On
On
On
On
On
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0
0
0
0
0 0
0 0
[3]
Doze Mode
DOZE = 0
DOZE = 1
On
Off
On
Off
On
Off
LSB
Stop Mode
Off
Off
Off
MOTOROLA
11-23
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