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When the receiver is first enabled and after the reception of a stop bit at the end of a
frame, an asynchronous search is initiated to find the leading edge of the next start
bit. (In the case of a framing error, because the stop bit has been somehow cor-
rupted, the start-bit validation logic may not operate (because there may not be a
negative edge to detect). As long as the voting logic is able to detect a start bit, the
receiver will be able to continue receiving characters following a framing error.)
The goal of this asynchronous search is to gain bit-time synchronization between the
serial data stream and the internal RT clock. Once synchronization has been estab-
lished, the RT clock controls where the UART perceives the bit-time boundaries to be.
The first step in locating a start bit is to find a sample where RXD is zero preceded by
four consecutive samples of logic ones. These five samples are called start-bit qualifi-
ers. Until the start-bit qualifiers are detected, the RT clock is reset to state RT1 after
each sample.
Once the qualifiers are found, the beginning of a start bit is tentatively assumed, and
successive samples are assigned successive RT state numbers. The next six sam-
ples are taken as start-bit verification samples. If even one of these is a logic one, the
low at RT1 is assumed to have been noise, and the asynchronous search is started
again. When the start-bit qualifiers and the start-bit verification requirements are met,
synchronization has been achieved, and the RT count state is used to determine the
position of bit-time boundaries.
During each bit time, including the start and stop bit times, data samples are taken to
determine the logic sense of the bit time. The samples are taken at RT9, RT10, and
RT11 or at RT8, RT9, and RT10, depending upon the synchronization of the incoming
data. The logic sense of the bit time is considered to be the majority of the three sam-
ples under consideration. At the end of a character reception, data is transferred from
the shift register to the parallel receiver register, with the corresponding flags updated
in the receiver register and the status register.
MOTOROLA
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11-18
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Freescale Semiconductor, Inc.
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MMC2001
REFERENCE MANUAL
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