Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual page 7

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9.3.2 Reset Sources............................................................................................... 9-2
9.3.3 Reset Sequence............................................................................................ 9-3
9.3.4 Reset Source/Chip Configuration Register (RSCR)...................................... 9-3
9.4 Time-of-Day Timer ........................................................................................... 9-4
9.4.1 TOD Operation .............................................................................................. 9-5
9.4.2 TOD in Low-Power Modes ............................................................................ 9-5
9.4.3 Time-of-Day Control/Status Register (TODCSR).......................................... 9-5
9.4.4 TOD Seconds Register (TODSR) ................................................................. 9-6
9.4.5 TOD Fraction Register (TODFR)................................................................... 9-6
9.4.6 TOD Seconds Alarm Register (TODSAR)..................................................... 9-7
9.4.7 TOD Fraction Alarm Register (TODFAR)...................................................... 9-7
9.5 Watchdog Timer............................................................................................... 9-8
9.5.1 Watchdog Timing Specifications ................................................................... 9-9
9.5.2 Watchdog Timer after Reset ......................................................................... 9-9
9.5.3 Watchdog Timer Service Operation .............................................................. 9-9
9.5.4 Watchdog Timer in Wait Mode ...................................................................... 9-9
9.5.5 Watchdog Timer in Doze Mode..................................................................... 9-9
9.5.6 Watchdog Timer in Stop Mode...................................................................... 9-9
9.5.7 Watchdog Timer in Debug Mode................................................................. 9-10
9.5.8 Watchdog Timer Programming Model......................................................... 9-10
9.6 Interval Timer (PIT) ........................................................................................ 9-11
9.6.1 PIT Operation .............................................................................................. 9-12
9.6.2 PIT as a "Set-and-Forget" Timer ................................................................. 9-12
9.6.3 PIT as a "Free-Running" Timer ................................................................... 9-13
9.6.4 Interval Timer Registers .............................................................................. 9-13
9.6.5 PIT Control/Status Register (ITCSR) .......................................................... 9-14
9.6.6 PIT Data Register (ITDR) ............................................................................ 9-15
9.6.7 PIT Alternate Data Register (ITADR) .......................................................... 9-16
9.6.8 PIT in Low-Power Modes ............................................................................ 9-16
9.6.9 PIT in Debug Mode ..................................................................................... 9-16
10.1 Overview ........................................................................................................ 10-1
10.2 Interrupt Controller Programming Model........................................................ 10-2
10.2.1 Interrupt Source Register (INTSRC) ........................................................... 10-2
10.2.2 Normal Interrupt Enable Register (NIER).................................................... 10-3
10.2.3 Fast Interrupt Enable Register (FIER)......................................................... 10-3
10.2.4 Normal Interrupt Pending Register (NIPND) ............................................... 10-4
10.2.5 Fast Interrupt Pending Register (FIPND) .................................................... 10-5
10.2.6 Interrupt Request Input Assignments .......................................................... 10-5
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TABLE OF CONTENTS
Title
SECTION 10
INTERRUPT CONTROLLER
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Page
MMC2001
REFERENCE MANUAL