Pit Control/Status Register (Itcsr; Watchdog Service Register; Pit Control And Status Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

WSR — Watchdog Service Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R 0 0 0 0
W
RESET:
0 0 0 0
C.3.9 PIT Control/Status Register (ITCSR)
ITCSR — Interval Timer Control and Status Register
31 30 29 28
R 0 0 0 0
W
RESET:
15 14 13 12
R 0 0 0 0
W
RESET:
Access this register with 32-bit loads and stores only.
STOP — Stop Mode Control
This bit controls the function of the PIT in stop mode
0 = PIT function is not affected while in stop mode
1 = PIT function is frozen while in stop mode
DOZE — Doze Mode Control
This bit controls the function of the PIT in doze mode
0 = PIT function is not affected while in doze mode
1 = PIT function is frozen while in doze mode
DBG — Debug Mode Control
This bit controls the function of the PIT in debug mode
0 = PIT function is not affected while in debug mode
1 = PIT function is frozen while in debug mode
MMC2001
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27 26 25
0 0 0
11 10 9
0 0 0

WATCHDOG SERVICE REGISTER

0 0 0
Figure C-13 Watchdog Service Register
27 26 25
0 0 0
11 10 9
0 0 0
Figure C-14 PIT Control and Status Register
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24 23 22 21
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
24 23 22 21
0 0 0 0
8 7 6 5
0
STOP DOZE DBG OVW
0 0 0
10001020
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
0 0 0 0
10001024
20 19 18 17
0 0 0 0
4 3 2 1
ITIE ITIF RLD
0 0 0 0
MOTOROLA
16
0
0
0
0
16
0
0
EN
0
C-11