Enabling Once Memory Breakpoints; Pipeline Information And Write-Back Bus Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

Only instructions actually executed cause the trace counter to decre-
ment, i.e., an aborted instruction does not decrement the trace counter
and does not invoke debug mode.

16.10.6 Enabling OnCE Memory Breakpoints

When the OnCE memory breakpoint mechanism is enabled with a breakpoint counter
value of zero, the device enters debug mode after completing the execution of the
instruction that caused the memory breakpoint to occur. In case of breakpoints on
instruction fetches, the breakpoint is acknowledged immediately after the execution of
the fetched instruction. In case of breakpoints on data memory addresses, the break-
point is acknowledged after the completion of the memory access instruction.

16.11 Pipeline Information and Write-Back Bus Register

A number of on-chip registers store the CPU pipeline status and are configured in a
single scan chain for access by the OnCE controller. The CPUSCR OnCE register
contains these processor resources, which are used to restore the pipeline and
resume normal device activity upon return from debug mode. These resources also
provide a mechanism for the emulator software to access processor and memory
contents. Figure 16-9 shows the block diagram of the pipeline information registers
contained in the CPUSCR.
Figure 16-9 CPU Scan Chain Register (CPUSCR)
MMC2001
REFERENCE MANUAL
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NOTE
32
31
WBBR
32
31
PSR
32
31
PC
16
15 0
CTL
OnCE™ DEBUG MODULE
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TDO
0
0
0
16
15 0
IR
TCK
TDI
MOTOROLA
16-17