Memory Address Latch (Mal); Once Memory Breakpoint Logic - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

DSCK
DSI
DSO
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Figure 16-7 OnCE Memory Breakpoint Logic
The address comparator generates a match signal when the address on the bus
matches the address stored in the breakpoint address base register, as masked with
individual bit masking capability provided by the breakpoint address mask register.
The address match signal and the access attributes are further qualified with the RCx
and BCx[4:0] control bits. This qualification is used to decrement the breakpoint
counter conditionally if its contents are non-zero. If the contents are zero, the counter
is not decremented and the breakpoint event occurs (ISBKPTx asserted).

16.8.1 Memory Address Latch (MAL)

The memory address latch (MAL) is a 32-bit register that latches the address bus on
every access.
MMC2001
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ADDR[31:0]
Memory Address Latch
Address Comparator
Address Base Register x
Address Mask Register x
Breakpoint Counter
COUNT=0
OnCE™ DEBUG MODULE
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ATTR
BC[4:0], RCx
MATCH
Memory
Breakpoint
Qualification
Breakpoint
Match
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Occurred
DEC
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ISBKPTx
MOTOROLA
16-13