Bus Signals; Address Bus (Addr[19:0]); Data Bus (Data[15:0]); Output Enable (Oe) - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

4.3 Bus Signals

This section describes the interface signals for external memory and peripherals.

4.3.1 Address Bus (ADDR[19:0])

The output address bus pins are used to address external devices. To minimize
power dissipation, they do not change state unless external memory is being
accessed.

4.3.2 Data Bus (DATA[15:0])

These pins provide the bidirectional data bus for external memory accesses.
DATA[15:0] are held in their previous logic state when there is no external bus activity.
This is accomplished with weak "keepers" inside the I/O buffers. They are also kept in
their previous state during hardware reset.

4.3.3 Output Enable (OE)

This active-low output signal indicates the bus access is a read and enables slave
devices to drive the data bus.

4.3.4 Read/Write Enable (R/W)

This active-low output signal indicates whether the current bus access is a read or
write.

4.3.5 Enable Byte 1 (EB1)

This active-low output pin is active during an operation to data bits DATA[7:0]. It may
be configured to assert for both read and write cycles, or for write cycles only.

4.3.6 Enable Byte 0 (EB0)

This active-low output pin is active during an operation to data bits DATA[15:8]. It may
be configured to assert for both read and write cycles, or for write cycles only.

4.3.7 Chip Selects (CS3, CS[2:0])

These output pins provide chip selects to external devices.

4.3.8 Internal ROM Disable (MOD)

This active-low input pin provides the capability of disabling the on-chip ROM and
forcing CS0 to be used to select an external boot ROM.

4.4 Exception Control Signals

4.4.1 Reset (RSTIN)

This active-low input signal is used to initiate a system reset. An external reset signal
resets the MMC2001 and most internal peripherals. The debug module is unaffected
by RSTIN; this function is provided through the TRST pin.
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SIGNAL DESCRIPTIONS
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MMC2001
REFERENCE MANUAL