Revision History - ST STM32F078CB Errata Sheet

STM32F078CB/RB/VB
3

Revision history

Date
12-Jun-2014
12-Oct-2016
Table 3. Document revision history
Revision
1 Initial release.
Added:
USART:
– Section 2.1.1: Start bit detected too soon when
sampling for NACK signal from the smartcard
– Section 2.1.2: Break request can prevent the
Transmission Complete flag (TC) from being set
– Section 2.1.3: nRTS is active while RE or UE = 0
– Section 2.1.4: Receiver timeout counter starting in
case of 2 stops bit configuration
I2C:
– Section 2.3.2: Spurious bus error detection in master
mode
– Section 2.3.8: 10-bit master mode: new transfer
cannot be launched if first part of the address has not
been acknowledged by the slave
SPI:
– Section 2.4.1: BSY bit may stay high when SPI is
disabled
2
– Section 2.4.2: BSY bit may stay high at the end of a
data transfer in slave mode
– Section 2.4.3: Wrong CRC transmitted in master
mode with delayed SCK feedback
– Section 2.4.4: CRC error in SPI slave mode if internal
NSS changes before CRC transfer
– Section 2.4.5: SPI CRC corrupted upon DMA
transaction completion by another peripheral
USB:
– Section 2.5.2: DCD (data contact detect) function not
compliant
RTC:
– Section 2.6.1: Spurious tamper detection when
disabling the tamper channel
– Section 2.6.2: A tamper event preceding the tamper
detect enable not detected
– Section 2.6.3: RTC calendar registers are not locked
properly
DocID026420 Rev 2
Revision history
Changes
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