ST STM32U575 Series Application Note
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ST STM32U575 Series Application Note

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AN5373
Application note
Getting started with STM32U575/585 MCU hardware development
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development
board features, such as power supply, clock management, reset control, boot mode settings and debug management.
This document details how to use the STM32U575xx and STM32U585xx microcontrollers (also named STM32U575/585) and
describes the minimum hardware resources required to develop an application using these MCUs.
Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces
and modes.
AN5373 - Rev 1 - June 2021
www.st.com
For further information contact your local STMicroelectronics sales office.

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  • Page 1 MCUs. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. AN5373 - Rev 1 - June 2021 www.st.com For further information contact your local STMicroelectronics sales office.

  • Page 2: General Information

    AN5373 General information General information ® This document applies to the STM32U575/585 Arm -based microcontrollers. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. AN5373 - Rev 1 page 2/37...

  • Page 3: Power Supply Management

    AN5373 Power supply management Power supply management Power supplies The STM32U575/585 devices require a 1.71 to 3.6 V operating voltage supply (V The independent supplies listed below, can be provided for specific peripherals: • = 1.71 V to 3.6 V is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks.

  • Page 4: Figure 1. Stm32U575Xx And Stm32U585Xx Power Supply Overview (No Smps)

    AN5373 Power supplies • REF- REF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage REF+ reference buffer (VREFBUF) when enabled. The VREF+ pin can be grounded when ADC and DAC are not active.

  • Page 5: Independent Analog Peripherals Supply

    AN5373 Power supplies Figure 2. STM32U575xQ and STM32U585xQ power supply overview (with SMPS) domain 2 x A/D converters VDDA 2 x comparators 2 x D/A converters VSSA 2 x operational amplifiers Voltage reference buffer VDDUSB USB transceiver domain DDIO2 DDIO2 VDDIO2 I/O ring PG[15:2]...

  • Page 6: Independent I/O Supply Rail

    AN5373 Power supplies ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate reference voltage lower than V is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC) REF+ signal.

  • Page 7: Voltage Regulator

    AN5373 Power supplies When the Backup domain is supplied by V (analog switch connected to the VDD pin), the following pins are available: • PC13, PC14 and PC15, that can be used as GPIO pins • PC13, PC14 and PC15, that can be configured by RTC or LSE (refer to the RTC section of the reference manual) •...

  • Page 8: Power Supply For I/O Analog Switches

    AN5373 Power supply schemes Dynamic Voltage scaling management Both LDO and SMPS regulators can provide four different voltages (voltage scaling) and can operate in all Stop modes. Both regulators also can operate in the following ranges: • Range 1 (1.2 V, 160 MHz), high performance: provides a typical output voltage at 1.2 V and is used when the system clock frequency is up to 160 MHz.

  • Page 9: Figure 3. Power Supply Scheme For Stm32U575X And Stm32U585X (Without Smps)

    AN5373 Power supply schemes • The VBAT pin can be connected to an external battery to preserve the content of the Backup domain: – When VDD is present, the external battery can be charged on VBAT through a 5 kΩ or 1.5 kΩ internal resistor.

  • Page 10: Figure 4. Power Supply Scheme For Stm32U575Xq And Stm32U585Xq (With Smps)

    AN5373 Power supply schemes Figure 4. Power supply scheme for STM32U575xQ and STM32U585xQ (with SMPS) Backup circuitry VBAT 1.65 – 3.6 V (LSE, RTC, TAMP, backup registers, backup SRAM) 3.3 V Power switch VDDUSB 100 nF VDDSMPS Voltage regulator 10 µF SMPS CORE VLXSMPS...

  • Page 11: Power Supply Sequence Between Vdda, Vddusb, Vddio2, And Vdd

    AN5373 Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD Power supply sequence between V , and V DDUSB DDIO2 2.3.1 Power supply isolation The devices feature a powerful reset system that ensures the main power supply (V ) has reached a valid operating range before releasing the MCU reset.

  • Page 12: Reset And Power-Supply Supervisor

    AN5373 Reset and power-supply supervisor Example of computation of the energy provided to the MCU during the power-down phase If the sum of decoupling capacitors on V is 10 μF and V drops below 1 V while V is still at 3.3 V, the energy remaining in the decoupling capacitors is: E = ½...

  • Page 13: Backup Domain Reset

    AN5373 Reset and power-supply supervisor The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

  • Page 14: Packages

    AN5373 Packages Packages Package summary The package selection must take into account the constraints that are strongly dependent upon the application. The list below summarizes the most frequent ones: • Amount of interfaces required: Some interfaces may not be available on some packages. Some interfaces combinations may not be possible on some packages.

  • Page 15: Pinout Summary

    AN5373 Pinout summary Pinout summary Table 2. Pinout summary for STM32U575/585 STM32U575xx and STM32U585xx STM32U575xQ and STM32U585xQ packages (without SMPS) packages (with SMPS) Pin name Specific I/Os PC14-OSC32_IN PC15- OSC32_OUT PH0-OSC_IN PH1-OSC_OUT System pins NRST PH3-BOOT0 Power pins VBAT VDDUSB VSSA VREF- VREF+...
  • Page 16 AN5373 Pinout summary Caution: STM32U575/585 packages with and without SMPS are not compatible, in almost all power supply pins of the above table. Example: VDDIO2 is the pin number 130 on SMPS package. Pin 130 on the package without SMPS is mapped to a VSS pin.

  • Page 17: Clocks

    AN5373 Clocks Clocks The following clock sources can be used to drive the system clock (SYSCLK): • HSI16: high-speed internal 16 MHz RC oscillator clock • MSIS: multi-speed internal RC oscillator clock • HSE: high-speed external crystal or clock, from 4 to 50 MHz •...

  • Page 18: External Crystal/Ceramic Resonator (Hse Crystal)

    AN5373 HSI16 clock Table 3. HSE/LSE clock sources Clock source Hardware configuration OSC_IN OSC_OUT External clock GPIO External souce OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors CL1 and CL2 values depend on the quartz. Refer to the application note Oscillator design guide for STM8AF/AL/S and STM32 microcontrollers (AN2867) for more details.

  • Page 19: Lse Clock

    AN5373 LSE clock The MSI clock can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails (see section' Clock security system (CSS)' in the reference manual). The MSI oscillator provides a low-cost (no external components) low-power clock source. In addition, when used in PLL‑mode with the LSE, the MSI provides a very accurate clock source that can be used by the USB OTG-FS peripheral, and feeds the PLL to run the system at the maximum speed 160 MHz.

  • Page 20: Boot Configuration

    TZEN option bit (TZEN = 0), the boot space is as detailed in the table below. Table 4. Boot modes when TrustZone is disabled (TZEN = 0) nBOOT0 nSWBOOT0 BOOT0 Boot address ST programmed FLASH_ FLASH_ Boot area option‑byte selection default value pin PH3 OPTR[27]...

  • Page 21: Embedded Bootloader And Rss

    0x0C00 0000 SECBOOTADD0[24:0] Embedded bootloader and RSS The embedded bootloader is located in the system memory and programmed by ST during production. It is used to reprogram the Flash memory by using the following serial interfaces: • USART: USART1 on pins PA9/PA10, USART2 on pins PA2/PA3, USART3 on pins PC10/PC11 •...

  • Page 22: Debug Management

    JTAG/serial-wire connector Debug tool Host Power supply STM32 board The Nucleo demonstration board embeds the debug tools (ST-LINK), so it can be directly connected to the PC through an USB cable. SWJ-DP (serial-wire and JTAG debug port) The SWJ-DP combines: •...

  • Page 23: Flexible Swj-Dp Pin Assignment

    AN5373 Pinout and debug port pins 6.2.2 Flexible SWJ-DP pin assignment After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins that are immediately usable by the debugger host. Note: The trace outputs are not assigned except if explicitly programmed by the debugger host. The table below shows the different possibilities for releasing some pins (see the reference manual for more details).

  • Page 24: Swj-Dp Connection With Standard Jtag Connector

    AN5373 Serial-wire debug (SWD) pin assignment 6.2.4 SWJ-DP connection with standard JTAG connector The figure below shows the connection between the device and a standard JTAG connector. Figure 9. JTAG connector implementation JTAG connector Connector 2 x 10 STM32U5 MCU VTREF nJTRST nTRST...

  • Page 25: Swd Port Connection With Standard Swd Connector

    AN5373 Serial-wire debug (SWD) pin assignment 6.3.2 SWD port connection with standard SWD connector The figure below shows the connection between the device and a standard SWD connector. Figure 10. SWD connector implementation NRST SWCLK/PA14 SWDIO/PA13 SWD connector STM32U5 device AN5373 - Rev 1 page 25/37...

  • Page 26: Recommendations

    AN5373 Recommendations Recommendations PCB (printed circuit board) For technical reasons, it is best to use a multilayer PCB, with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.

  • Page 27: Other Signals

    AN5373 Other signals The figure below shows the typical layout of such a VDD/VSS pin pair. Figure 11. Typical layout for VDD/VSS pin pair Via to VDD Via to VSS STM32 Other signals When designing an application, the EMC performance can be improved by closely studying the following: •...

  • Page 28: Reference Design

    AN5373 Reference design Reference design Description The reference design shown in the following figures is based on an STM32U575/585 device in LQFP144. This reference design can be tailored to any STM32U575/585 device with a different package, using the pin correspondence given in Section 8.2 Clock Two clock sources are used for the MCU (see...

  • Page 29: Component References

    Used for LSE Quartz 16 MHz Used for HSE Used to limit the current on VBAT pin Resistor 10 KΩ R2, R3, R4 Used for the ST-LINK interface Switch Used to select the right boot mode AN5373 - Rev 1 page 29/37...

  • Page 30: Figure 12. Stm32U575Xxx Reference Design (Without Smps)

    AN5373 Component references Figure 12. STM32U575xxx reference design (without SMPS) AN5373 - Rev 1 page 30/37...

  • Page 31: Figure 13. Stm32U575Xxq Reference Design (With Smps)

    AN5373 Component references Figure 13. STM32U575xxQ reference design (with SMPS) AN5373 - Rev 1 page 31/37...

  • Page 32: Revision History

    AN5373 Revision history Table 10. Document revision history Date Version Changes 21-Jun-2021 Initial release. AN5373 - Rev 1 page 32/37...

  • Page 33: Table Of Contents

    AN5373 Contents Contents General information ............. . . 2 Power supply management .
  • Page 34 AN5373 Contents Embedded bootloader and RSS ..........21 Debug management .

  • Page 35: List Of Tables

    AN5373 List of tables List of tables Table 1. Package summary for STM32U575/585 ........... 14 Table 2.

  • Page 36: List Of Figures

    AN5373 List of figures List of figures Figure 1. STM32U575xx and STM32U585xx power supply overview (no SMPS) ......4 Figure 2.
  • Page 37 ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’...

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