Cec; Transmission Blocked When Transmitted Start Bit Is Corrupted; Tsc; Inhibited Acquisition In Short Transfer Phase Configuration - ST STM32F078CB Errata Sheet

STM32F078CB/RB/VB
2.9

CEC

2.9.1

Transmission blocked when transmitted start bit is corrupted

Description
When the HDMI-CEC communication start bit transmitted by the device is corrupted by
another device on the CEC line, the CEC transmission is stalled.
This failure is unlikely to happen as the CEC start bit corruption by another device can only
occur if that device does not respect the CEC communication protocol.
The start bit timing standard tolerances are shown in
device by driving the CEC line low (reference point). After 3.7 ms, the device releases the
CEC line and starts checking its level. The following conditions must be met for the start bit
to be valid:
• the CEC line goes high no later than 3.9 ms (4.05 ms with extended tolerance) from the
reference point
• a falling edge on the CEC line does not occur earlier than 4.3 ms (4.15 ms with extended
tolerance) from the reference point
If one of these conditions is not met, the transmission is aborted and never automatically
retried. No error flag is set and the TXSOM (Tx Start Of Message) bit is not cleared.
high impedance
low impedance
Workaround
A way to work this limitation around is for the system-level CEC application software to start
a time-out counter when setting TXSOM bit and stop it upon TXBR or TXEND event. In case
of time-out, the HDMI-CEC functional block is disabled then enabled, by setting the CECEN
bit in CEC_CR register to 0 then to 1. This clears the TXSOM bit.
2.10

TSC

2.10.1

Inhibited acquisition in short transfer phase configuration

Description
The GPIO input buffer is masked outside the transfer window time and then sampled twice
before being checked for the acquisition. This check is performed on the last touch sensing
clock cycle of the charge transfer phase. When the charge transfer duration is less than
three clock cycles, the acquisition is inhibited.
Figure 1. HDMI-CEC start bit format with tolerances
CEC line
0
Reference point
DocID026420 Rev 2
Description of device limitations
Figure 1. The start bit is initiated by the
3.5 3.7 3.9 4.3 4.5 4.7
time [ms]
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