Summary Of Device Limitations - ST STM32F078CB Errata Sheet

Summary of device limitations

1 Summary of device limitations
The following table gives a quick references to all documented device limitations of
STM32F078CB/RB/VB and their status:
A = workaround available
N = no workaround available
P = partial workaround available
"-" grayed = limitation not existing / limitation fixed
Function Section
2.1.1
2.1.2
2.1.3
USART
2.1.4
2.1.5
2.1.6
GPIO 2.2.1
2.3.1
2.3.2
2.3.3
2.3.4
I2C
2.3.5
2.3.6
2.3.7
2.3.8
4/21
Table 2. Summary of device limitations
Start bit detected too soon when sampling for NACK signal from the
smartcard
Break request can prevent the Transmission Complete flag (TC) from
being set
nRTS is active while RE or UE = 0
Receiver timeout counter starting in case of 2 stops bit configuration
USART4 transmission does not work on PC11
Last byte written in TDR might not be transmitted if TE is cleared just after
writing in TDR
GPIOx locking mechanism not working properly for GPIOx_OTYPER
register
Wrong data sampling when data set-up time (tSU;DAT) is shorter than one
I2CCLK period
Spurious bus error detection in master mode
10-bit slave mode: wrong direction bit value after Read header reception
10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong
slave address detection
Wakeup frames may not wakeup the MCU mode when STOP mode entry
follows I2C enabling
Wakeup frame may not wakeup from STOP if tHD;STA is close to HSI
startup time
Wrong behavior in Stop mode when wakeup from Stop mode is disabled in
I2C
10-bit master mode: new transfer cannot be launched if first part of the
address has not been acknowledged by the slave
DocID026420 Rev 2
Limitation
STM32F078CB/RB/VB
Status
Rev. 'Y', '1'
N
A
A
A
A
A
P
P
A
A
N
A
P
A
A