ST STM32F078CB Errata Sheet page 5

STM32F078CB/RB/VB
Function Section
2.4.1
2.4.2
2.4.3
2.4.4
SPI
2.4.5
2.4.6
2.5.1
USB
2.5.2
2.6.1
RTC 2.6.2
2.6.3
2.7.1
ADC
2.7.2
COMP 2.8.1
CEC 2.9.1
TSC 2.10.1
2.11.1
IWDG
2.11.2
Table 2. Summary of device limitations (continued)
BSY bit may stay high when SPI is disabled
BSY bit may stay high at the end of a data transfer in slave mode
Wrong CRC transmitted in master mode with delayed SCK feedback
CRC error in SPI slave mode if internal NSS changes before CRC transfer
SPI CRC corrupted upon DMA transaction completion by another
peripheral
In I2S slave mode: WS level must be set by the external master when
enabling the I2S
The USB BCD functionality limited below -20°C
DCD (data contact detect) function not compliant
Spurious tamper detection when disabling the tamper channel
A tamper event preceding the tamper detect enable not detected
RTC calendar registers are not locked properly
Overrun flag not set if EOC reset coincides with new conversion end
ADEN bit cannot be set immediately after the ADC calibration
Long VREFINT scaler startup time after power on
Transmission blocked when transmitted start bit is corrupted
Inhibited acquisition in short transfer phase configuration
RVU, PVU and WVU flags are not reset in STOP mode
RVU, PVU and WVU flags are not reset with low-frequency APB
DocID026420 Rev 2
Summary of device limitations
Limitation
Status
Rev. 'Y', '1'
A
A
A
A
P
A
N
N
P
A
A
A
A
N
P
P
A
N
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