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ADP1046A 100Watt
Evaluation board
Figure 30 - CS2 OCP condition, with 2.5ms debounce time, action set to disable
SR1, SR2, and OrFET
Yellow trace: Output current
Red and Blue traces: SR1 and SR2 signals
Green: OrFET GATE signal (inverted)
Additional things to try:
a)
Setting a different light load thresholds and measuring its effect on efficiency.
b)
Using the line impedance feature to simulate the voltage drop through a 2 foot output cable.
c)
Reducing the current sense resistor value (R17) and changing the range of the full scale voltage drop on CS2+ and
CS2-.
d)
Change the CS2 averaging speeds and see the effect on transient response from DCM to CCM.
e)
Setting different OCP limits and setting a different response such as disable all PWMs
Figure 31 - Latching short circuit protection
Upper trace: Output current, 10A/div, 500ms/div
Lower trace: Output Voltage, 5V/div, 500ms/div
Rev. 1.3 | Page 21 of 55
PRD1386
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