Analog Devices ADP1046A User Manual page 18

ADP1046A 100Watt
Evaluation board
Figure 25 - Primary current with programmed imbalance between PWMs (less
than 180μs), 8A load
C. CS1 Fast OCP: Figure 27 and Figure 28 show the CS1 fast OCP tripping under a shorted output.
In this test the CS1 pulse by pulse current limit was tested during a shorted output. A shutdown was programmed
after 4 repetitive OCP limits were triggered.
Figure 24 - PWM Settings for programmed 75ns Volt-Second imbalance on OUTB and OUTC
Figure 26 - Primary current after Volt Second Balance implemented, 8A load
Rev. 1.3 | Page 18 of 55
PRD1386