Advantech PCA-6145B Manual page 77

Table C.11: DMA channel assignments
Channel
0
1
2
3
4
5
6
7
Table C.12: DMA controller registers
Address
0C0
0C2
0C4
0C6
0C8
0CA
0CC
0CE
0D0
0D2
0D4
0D6
0D8
0DA
0DC
0DE
Table C.13: DMA Page Addresses
Page register
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 5
DMA Channel 6
DMA Channel 7
Refresh
Function
Spare (8-bit transfer)
SDLC (8-bit transfer)
Floppy disk (8-bit transfer)
Spare (8-bit transfer)
Cascade for DMA controller 1
Spare (16-bit transfer)
Spare (16-bit transfer)
Spare (16-bit transfer)
Command code
CH0 base and current address
CH0 base and current word count
CH1 base and current address
CH1 base and current word count
CH2 base and current address
CH2 base and current word count
CH3 base and current address
CH3 base and current word count
Read status register/Write command register
Write mode register
Read temporary register/Write command register
Write mode register
Clear byte pointer flip-flop
Read status register/Write command register
Write mode register
Write all mask register bus
I/O Address
0087
0083
0081
0082
008B
0089
008A
008F
67 Appendix C