SOLTEK SL-B9D-FGR Manual page 63

SL-B9D-FGR
LDT & PCI Bus Control:
To press< Enter > on LDT & PCI Bus Control will reveal the following
item(s).
Upstream LDT Bus
Downstream LDT Bus
LDT Bus Frequency To set LDT Bus Frequency.
PCI1 Master 0 WS
PCI1 Post Write To enable (default) / disable the support of PCI1 Post
Memory Hole To enabled / disabled (default) the support of
VLink Data Rate To set VLink Data Rate.
Init Display First Initialize the AGP video display before initializing any
System BIOS
Cacheable
To set Upstream LDT BUS Width.
Width Choices: 8 bit; 16 bit
To set Downstream LDT BUS Width.
Width Choices: 8 bit; 16 bit
Choices: 200MHz; 400MHz; 600MHz; 800MHz;1G
To enable (default) / disable the support of PCI1
Write
Master 0 Wait State Write.
Write.
Memory Hole which is reserved for ISA card.
Choices: Disabled; 15MB-16MB
Choices: 8X; 4X
other display device on the system. Thus the AGP
display becomes the primary display.
Selecting Enabled allows caching of the system
BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
Auto
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Chapter 4 BIOS Setup