Congatec conga-QEVAL/Qseven 2.0 User Manual page 19

Pin Signal Description
109 eDP0_TX2- eDP Primary channel 2-
/ LVDS_A2- LVDS Primary channel 2-
LVDS_PPEN LVDS Power enable
111
eDP0_TX3+ eDP Primary channel 3+
113
/ LVDS_A3+ LVDS Primary channel 3+
eDP0_TX3- eDP Primary channel 3-
115
/ LVDS_A3- LVDS Primary channel 3-
117 GND Power Ground
eDP0_AUX+ eDP Primary Auxilliary channel+
119
/ LVDS_A_CLK+ LVDS Primary channel CLK+
121 eDP0_AUX- eDP Primary Auxilliary channel-
/ LVDS_A_CLK- LVDS Primary channel CLK-
123 LVDS_BLT_CTRL PWM Backlight brightness
/ GP_PWM_OUT0 General Purpose PWM Output
125 LVDS_DID_DAT DDC Display ID Data line
/ GP2_I2C_DAT General Purpose I2C Data line
127 LVDS_DID_CLK DDC Display ID Clock line
/ GP2_I2C_CLK General Purpose I2C Clock line
129 CAN0_TX CAN TX Output for CAN Bus Channel 0
131 DP_LANE3+ DisplayPort differential pair line lane 3+.
/ TMDS_CLK+ Multiplexed with TMDS differential pair clock+
133 DP_LANE3- DisplayPort differential pair line lane 3-.
/ TMDS_CLK- Multiplexed with TMDS differential pair clock-
135 GND Power Ground
137 DP_LANE1+ DisplayPort differential pair line lane 1+
/ TMDS_LANE1+ Multiplexed with TMDS differential pair lane1+
139 DP_LANE1- DisplayPort differential pair line lane 1-
/ TMDS_LANE1- Multiplexed with TMDS differential pair lane1-
141 GND Power Ground
143 DP_LANE2+ DisplayPort differential pair line lane 2+
/ TMDS_LANE0+ Multiplexed with TMDS differential pair line lane0+
145 DP_LANE2- DisplayPort differential pair line lane 2-
/ TMDS_LANE0- Multiplexed with TMDS differential pair line lane0-
147 GND Power Ground
149 DP_LANE0+ DisplayPort differential pair line lane 0+
/ TMDS_LANE2+ Multiplexed with TMDS differential pair lane2+
151 DP_LANE0- DisplayPort differential pair line lane 0-
/ TMDS_LANE2- Multiplexed with TMDS differential pair lane2-
153 DP_HDMI_HPD# Hot plug detection
155 PCIE_CLK_REF+ PCI Express Reference Clock+
157 PCIE_CLK_REF- PCI Express Reference Clock-
159 GND Power Ground
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Pin Signal
110 eDP1_TX2-
/ LVDS_B2-
112 LVDS_BLEN
114 eDP1_TX3+
/ LVDS_B3+
116 eDP1_TX3-
/ LVDS_B3-
118 GND
120 eDP1_AUX+
/ LVDS_B_CLK+
122 eDP1_AUX-
/ LVDS_B_CLK-
124 GP_1-Wire_Bus
126 eDP0_HPD#
/ LVDS_BLC_DAT
128 eDP1_HPD#
/ LVDS_BLC_CLK
130 CAN0_RX
132 RSVD (Differential)
134 RSVD (Differential)
136 GND
138 DP_AUX+
140 DP_AUX-
142 GND
144 RSVD (Differential Pair)
146 RSVD (Differential Pair)
148 GND
150 HDMI_CTRL_DAT
152 HDMI_CTRL_CLK
154 DP_HPD
156 PCIE_WAKE#
158 PCIE_RST#
160 GND
QEV2m11
Description
eDP Secondary channel 2-
LVDS Secondary channel 2-
LVDS Backlight enable
eDP Secondary channel 3+
LVDS Secondary channel 3+
eDP Secondary channel 3-
LVDS Secondary channel 3-
Power Ground
eDP Secondary Auxiliary channel CLK+
LVDS Secondary channel CLK+
eDP Secondary Auxiliary channel CLK-
LVDS Secondary channel CLK-
General Purpose 1-wire bus interface
SSC clock chip data line. Can be used as eDP
primary hotplug detect
SSC clock chip clock line. Can be used as eDP
secondary hotplug detect
CAN RX Input for CAN Bus Channel 0
Reserved
Reserved
Power Ground
DisplayPort auxiliary channel
DisplayPort auxiliary channel
Power Ground
Reserved
Reserved
Power Ground
DDC based control signal (data) for HDMI/DVI
device.
DDC based control signal (clock) for HDMI/DVI
device.
DisplayPort Hot Plut Detect
PCI Express Wake event
Reset Signal for external devices
Power Ground
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