Specifications - Analog Devices ADP50460008 Owner's Manual

ADI Confidential

SPECIFICATIONS

T = 25°C, V = V = 3.6 V, V
J VBATT VDD
Table 1.
Parameter
INPUT SUPPLY VOLTAGE RANGE
Minimum Power-Up V Voltage
VBATT
QUIESCENT CURRENT
Operating Quiescent Current
VBATT
VDD
Channel 1 Power Save Mode (PSM),
I + I
VBATT VDD
VDDIO
PVIN2
PVIN3
PVIN4
VIN5
PVIN6
VIN8
System Lockout Current, I
VBATT
BACKUP BATTERY MODE
BU3INT Operating Quiescent Current
(Backup Battery Mode)
Lockout Current
(Backup Battery Mode)
UVLO
System Undervoltage Lockout
Threshold (Rising)
Hysteresis
VDD Undervoltage Lockout Threshold
(Rising)
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency 1
Switching Frequency 2
LOGIC INPUTS
EN Pin
Low Level Threshold
High Level Threshold
SCL and SDA Pins
Low Level Threshold
High Level Threshold
= 3.3 V, unless otherwise noted.
VDDIO
Symbol Min
V 2.1
IN
V 2.3
POWER-UP MIN
I
Q(VBATT_OP1)
I
Q(VBATT_OP2)
I
Q(VDD_OP1)
I
Q(VDD_OP2)
I
Q(PSM_OP)
I
Q(VDDIO)
I
Q(PVIN2)
I
Q(PVIN3)
I
Q(PVIN45)
I
Q(VIN5)
I
Q(PVIN6)
I
Q(VIN8)
+ I I
VDD Q(LOCKOUT)
I
Q(STNBYBACKUP)
I
Q(LOCKBACKUP)
V 2.522
UVLO_SYS1
2.2
V
HSY_UVLO_SYS
V
UVLO_VDD
V
HYS(UVLO_VDD)
f 2.125
SW1
2
f 1.12
SW2
1.0625
V
IL(EN)
V 0.7 × V
IH(EN)
V
IL(I2C)
V 0.7 × V
IH(I2C)
Typ Max
3.6 5.5
13
20 40
3.9
4.75 7
60
0.25
1
1
1
1
1
32
2
1.5
0.1
2.6 2.75
2.3 2.43
0.2
2.19
0.1
2.5 2.875
2.5 3
1.25 1.38
1.25 1.4275
0.3 × V
VREGO
VREGO
0.3 × V
VDDIO
VDDIO
Rev. Sp0 | Page 3 of 60
ADP50460008
Unit Test Conditions/Comments
V Includes VBATT, PVIN2, PVIN3, PVIN4,
PVIN6, VIN8, and VDDIO
V
µA No switching, EN = high
µA No switching, EN = high, V
mA No switching, EN = high
mA No switching, EN = high, V
µA No switching, EN = low, V
4.2 V, 5.5 V
µA V = V = V = 3.3 V
VDDIO SCL SDA
µA No switching, V = V
VBATT
EN = high
µA No switching, V = V
VBATT
EN = high
µA No switching, V = V
VBATT
EN = high
µA V = V = 3.6 V
VBATT VDD
µA No switching, V = V
VBATT
EN = high
µA No load, V = V + 0.5 V, V
IN8 OUT8
µA V = V = 1.8 V, EN = low
VBATT VDD
µA Includes RTCOSC, RTC logic, and
1
UVLO_RTC; V = V
VBATT
V = 2.0 V
BU3INT
µA
Battery voltage disconnected from
VBATT node; V = 1.0 V
BU3INT
V See Table 74, Register OPT_UVLO_SYS_R,
Bit 7 (SEL_VTH_R) = 0b
V See Table 74, Register OPT_UVLO_SYS_R,
Bit 7 (SEL_VTH_R) = 1b
V
V
V
MHz
MHz −10°C ≤ T ≤ +85°C
J
MHz
MHz −10°C ≤ T ≤ +85°C
J
V V = 3.2 V, −10°C ≤ T
VREGO
V V = 3.2 V, −10°C ≤ T
VREGO
V V = 3.3 V, −10°C ≤ T
VDDIO
V V = 3.3 V, −10°C ≤ T
VDDIO
= 5.5 V
VBATT
= 5.5 V
VDD
= 3.0 V,
VBATT
= V = 3.6 V,
VDD PVIN2
= 3.6 V,
VDD
= 3.6 V,
VDD
= 3.6 V,
VDD
= 3.3 V
OUT8
= 0 V;
VDD
≤ +85°C
J
≤ +85°C
J
≤ +85°C
J
≤ +85°C
J