Analog Devices ADP50460008 Owner's Manual page 25

ADI Confidential
2
I C Interface Timing
2
The ADP5046 includes an I
control of the power management blocks and for reading back
the RTC registers and system status. The I
(0011 0000 (binary) in write mode), and the subaddress is used
to select any of the user registers that are implemented. The
ADP5046 sends the data from the register denoted by the
subaddress. Note that the ADP5046 does not respond to general
calls. The ADP5046 accepts multiple masters, but if the device is
in read mode, this access is limited to one master until the data
transmission is complete. Table 12 shows a complete map of the
available registers. See Figure 45 for a write mode timing diagram;
SCL
SDA
NOTES
1. MAXIMUM SCL FREQUENCY 400kHz
2. NO RESPONSE TO GENERAL CALL
SCL
SDA
0 1
CHIP ADDRESS
OUTPUT BY PROCESSOR
OUTPUT BY ADP5046
NOTES
1. MAXIMUM SCL FREQUENCY 400kHz
2. NO RESPONSE TO GENERAL CALL
SCL
SDA
0 1 1 0 0 0
CHIP ADDRESS
OUTPUT BY PROCESSOR
OUTPUT BY ADP5046
NOTES
1. MAXIMUM SCL FREQUENCY 400kHz
2. NO RESPONSE TO GENERAL CALL
C-compatible serial interface for
2
C chip address is 0x30
0 1 1 0 0 0 0 0
CHIP ADDR ESS
OUTPUT BY PROCESSOR
OUTPUT BY ADP5046
Figure 45. I
1 0 0 0 0 0
SUBADDRESS
2
Figure 46. I C Read from Registers with No Read Status Bits
0 0
SUBADDRESS
2
Figure 47. I C Read from Registers with Read Status Bits
Figure 46 and Figure 47 show diagrams of read mode timing.
The I 2 C interface operates at clock frequencies of up to 400 kHz.
The registers from Address 32 to Address 62 have a special
status flag (Bit 7) that can be read to determine if valid data is
present in the register. If the status bit is 0, the data is not yet
valid; therefore, the read operation must be repeated until the
status bit changes to 1, indicating that the data is valid. Before
the status bit changes to 1, a minimum of two read operations
is required. The required number of reads depends on the
relationship between the RTC clock frequency and the SCL
frequency. For example, when the SCL frequency is 400 kHz,
the minimum number of reads is approximately 6.
SUBADDR ESS
2 C Write to Registers
0 1 1 0 0 0 0
CHIP ADDRESS
0 1 1 0 0 0 0 1 0
CHIP ADDRESS
READ DATA
Rev. Sp0 | Page 25 of 60
WRITE DATA
1
READ DATA
1
READ DATA
ADP50460008