Wake-Up Sequence - Analog Devices ADP50460008 Owner's Manual

ADI Confidential

WAKE-UP SEQUENCE

The ADP5046 wake-up sequence is shown in Figure 33. Wake-up
starts when the main battery voltage rises above the system under-
voltage level (UVLO_SYS). The ADP5046 remains in standby
mode as long as the EN pin is set to a logic level low. In this
mode, the PSM boost regulator and the low quiescent current
regulator keep alive LDO are active.
A high logic level at the EN pin initiates the turn-on sequence,
which starts by checking that there are no fault conditions and
that the internal biasing circuits have reached the nominal
operating conditions.
MAIN BATTERY
CONNECT
UVLO?
YES
VBATT > UVLO_SYS
KEEP ALIVE LDO
AND
CHANNEL 1 (PSM)
ON
POCO
STANDBY?
EN = H
YES
REF_GOOD
OK?
YES
TEMP < 160°C
VDD > 2.19V
VREF > 1.0V
ENABLE DELAY
ON
CH 2, CH 3,
CH 6 (OPT),
CH 8 (OPT) ON
NO
VBATT < UVLO_SYS
NO
EN = L
TEMP > 160°C
NO VDD < 2.19V
VREF < 1.0V
EVENT TIMER
0.5s
Figure 33. Wake-Up Sequence
Rev. Sp0 | Page 19 of 60
If the state machine does not detect a fault condition, the
regulator turn-on sequence begins after the enable turn-on
delay has elapsed.
The regulators (except Channel 4, Channel 5, and Channel 7)
turn on according to the predefined timing sequence. The
ADP5046 remains in the wake-up state as long as the EN pin is
at logic level high and no undervoltage condition is detected.
An undervoltage condition triggers the power-down sequence
(instant shutoff system), where the active regulators are turned
off and the ADP5046 waits for a new activation from the EN pin.
WAKE-UP NO
OPERATION?
EN = H
YES
EN = L
OVP?
DISABLE DELAY
ON
YES
V
OVP
>125%
OVP DELAY
ON
CH 2, CH 3,
CH 6, CH 8 OFF
ADP50460008
NO NO
UVP?
V V
OVP UVP
<125% >67%
YES
V
UVP
<67%
UVP DELAY
ON