Theory Of Operation; Introduction; Enable - Analog Devices ADP50460008 Owner's Manual

ADP50460008

THEORY OF OPERATION

INTRODUCTION

The ADP5046 is a highly integrated power management unit
(PMU) that features six switching regulators, two LDOs, a load
switch, a backup battery charger, a real-time clock, and a 32 kHz
oscillator. The PMU can be activated by a logic level high on the
EN pin or following an alarm event that is generated by the
countdown timer.
The ADP5046 also includes a slave-only I
communication with an external processor. Through the I
interface, it is possible to change parameters, such as the output
voltage, soft start, and sequencing of the regulators, and to set
the RTC registers and the countdown alarm. Some parameters
are factory defined to address different system requirements
that must be available before the system powers up and programs
the PMU registers. Contact an Analog Devices, Inc., representative
for information about the factory programming options that are
available.

ENABLE

The enable pin (EN) controls the on and off states of the ADP5046.
A high logic level on the EN pin turns the device on, whereas
a low logic level turns the device off.
A low-to-high transition on the EN pin starts the activation circuit
by enabling the reference block after three 32 kHz clock cycles.
Then the activation circuit checks for fault conditions, such as
the V voltage being below the threshold, the temperature
VDD
being too high, the oscillator not running, and the reference
voltage being below the nominal level. If no fault is detected, the
power-up sequence is generated after the turn-on delay time,
which is factory programmed for each regulator channel.
2
C interface for
2 C
Rev. Sp0 | Page 18 of 60
The default power-up sequence of the regulators is Channel 2
first, Channel 3 second, Channel 6 third, and Channel 8 fourth,
while Channel 1 stays in PSM mode. No regulator sequence is
generated when the device is turned off (EN = low) except the
Channel 1 PSM mode. All the active regulators, except Channel 3,
are turned off simultaneously. Channel 3 is turned off after the
disable delay time (default = 30 ms), upon a high-to-low
transition at the EN pin.
The ADP5046 can also turn on after the countdown timer
decrements to 0 and an alarm is generated. Then Bit 6
(TIMEOUT) in Register RTCAL_HR (Address 35) is
set to 1.
VDD
VREGO
LEVEL
EN
SHIFTER
Figure 31. Enable Circuit
EN
TYP 3 CLK
INTERNAL
REF ENABLE
REF_GOOD
CHANNEL 1 ON
Figure 32. Enable Timings
ADI Confidential
VDD
TO
POWER
SEQUENCER
CONTROL
REF_GOOD EN_REF
DISABLE
DELAY TIME
MIN 500µs
TYP 4 CLK
2 CLK + ENABLE
DELAY TIME