Pin Configuration And Function Descriptions - Analog Devices ADP50460008 Owner's Manual

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions
Pin
No. Mnemonic Description
1A SW7 Switching Node for Channel 7 (Boost Regulator and LED Driver). Leave this pin open if Channel 7 is not used.
1B PVIN2 Input Power Supply for Channel 2 (Buck-Boost Regulator).
1C SWA2 Primary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
1D PGND2 Power Ground for Channel 2 (Buck-Boost Regulator).
1E SWB2 Secondary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
1F VOUT2 Output Voltage for Channel 2 (Buck-Boost Regulator).
1G PVIN6 Input Power Supply for Channel 6 (Buck Regulator).
1H SW6 Switching Node for Channel 6 (Buck Regulator).
2A PGND7 Power Ground for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
2B PVIN2 Input Power Supply for Channel 2 (Buck-Boost Regulator).
2C SWA2 Primary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
2D PGND2 Power Ground for Channel 2 (Buck-Boost Regulator).
2E SWB2 Secondary-Side Switching Node for Channel 2 (Buck-Boost Regulator).
2F VOUT2 Output Voltage for Channel 2 (Buck-Boost Regulator).
2G FB6 Feedback for Channel 6 (Buck Regulator).
2H PGND6 Power Ground for Channel 6 (Buck Regulator).
3A BLGND7 Analog Ground for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
3B OVP7 Overvoltage Sensing for Channel 7 (Boost Regulator and LED Driver). Connect this pin to ground if Channel 7 is not used.
3C ISET7 LED Current Reference for Channel 7 (Boost Regulator and LED Driver). Leave this pin open if Channel 7 is not used.
3D ALMO Alarm Output. This pin can be connected to an external processor. This pin is also a VREGO domain CMOS output.
Leave this pin open if ALMO is not used.
3E TEST2 Test Pin. Connect to ground.
3F EN Enable. Logic high turns on the PMU.
3G FB4 Feedback for Channel 4 (Buck Regulator).
3H PGND4 Power Ground for Channel 4 (Buck Regulator).
1 2 3
SW7 PGND7 BLGND7 VIN5
A
PVIN2 PVIN2 OVP7 LSTR7
B
SWA2 SWA2 ISET7 TEST4
C
PGND2 PGND2 ALMO VDDIO
D
SWB2 SWB2 TEST2 SDA
E
VOUT2 VOUT2 EN TEST1
F
PVIN6 FB6 FB4 POCO
G
SW6 PGND6 PGND4 SW4
H
Figure 3. Pin Configuration (Top View)
Rev. Sp0 | Page 11 of 60
4 5 6 7
VOUT5 PGND3 SW3
DL3 PGND3 SW3
TEST3 FB3 VIN8 VOUT8
GND GND VOUT1 VOUT1
SCL VDD SW1
VBATT VREGO SW1
CLKO RTCGND PGND1 PGND1
PVIN4 XOUT XIN BU3INT
ADP50460008
8
PVIN3
PVIN3
SW1
SW1