Undervoltage Protection (Uvp) And Overvoltage Protection (Ovp); Vrego Keep Alive Ldo Circuit; Uvlo_Sys Circuit; Uvlo_Rtc Circuit - Analog Devices ADP50460008 Owner's Manual

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UNDERVOLTAGE PROTECTION (UVP) AND
OVERVOLTAGE PROTECTION (OVP)
Channel 2, Channel 3, Channel 6, and Channel 8 have individual
undervoltage detection and status flags in Register UVPST at
Address 12 (Bit 7, Bit 5, Bit 2, and Bit 1). In addition, Channel 2,
Channel 3, Channel 6, and Channel 7 have individual overvoltage
detection and status flags in Register OVPST at Address 13
(Bits[2:1] for Channel 3 and Channel 2, respectively; and Bits[6:5]
for Channel 7 and Channel 6, respectively). Channel 4 has a fault
status flag (Bit 3 in the UVPST register) that can indicate both
UVP and OVP status.
An undervoltage condition occurs when a regulator output
voltage falls below the regulation value for a time that is longer
than the undervoltage detection delay.
The UVP thresholds for Channel 2, Channel 3, Channel 4,
Channel 6, and Channel 8 are 67% of their respective nominal
output voltage. The undervoltage detection delay is factory
programmed, and it can be set to 0 ms (no delay), 78 ms,
200 ms, or disabled (no undervoltage detection).
If an undervoltage event is detected on Channel 2, Channel 3,
Channel 6, or Channel 8, all the enabled channels are turned off
and the affected channel status flag in the UVPST register (Bit 1
for Channel 2, Bit 2 for Channel 3, Bit 5 for Channel 6, and Bit 7
for Channel 8) is reset. The UVPST register is cleared after its
content is read once, and then the state machine waits for the
enable input pin (EN) to be set low.
If either an undervoltage or overvoltage event is detected on
Channel 4, both Channel 4 and Channel 5 are turned off.
Channel 2, Channel 3, Channel 6, and Channel 7 have individual
overvoltage detection and status flags in the OVPST register
(Bits[2:1] for Channel 3 and Channel 2, respectively; and Bits[6:5]
for Channel 7 and Channel 6, respectively). An overvoltage
condition occurs when a regulator output voltage is greater than
the regulation threshold for a time longer than the overvoltage
detection delay.
Channel 7 is turned off and the status flag (Register OVPST, Bit 6)
is set if an overvoltage event is detected at its output. The OVPST
register is cleared after its content is read once. OVP can be
triggered regardless of the status register content.
If an overvoltage event is detected on Channel 2, Channel 3,
or Channel 6, all of the enabled channels are turned off and the
affected channel status flag in Register OVPST (Bit 1 for Channel 2,
Bit 2 for Channel 3, and Bit 5 for Channel 6) is set. The OVPST
register is cleared after its content is read once, and then the state
machine waits for the enable input pin (EN) to be set low.
The overvoltage detection delay is factory programmed and
can be set to 0 ms (no delay), 1.2 ms, 3.3 ms, or disabled (no
overvoltage detection). The overvoltage detection delay setting
is also valid for the undervoltage detection delay for Channel 4.
In other words, the setting of undervoltage detection delay is
not applied to Channel 4.
The OVP thresholds for Channel 2, Channel 3, Channel 4, and
Channel 6 are 125% of their nominal output voltage. The OVP
for Channel 7 is monitored at the OVP7 pin, and the threshold
is 24.3 V typical.
Table 11. UVP and OVP Mapping for Each Channel
CH 1
UVP No
OVP No
1
A yes means that this feature is available; a no means that it is not available.

VREGO KEEP ALIVE LDO CIRCUIT

The voltage of the VREGO pin is regulated by the keep alive
LDO to have a fixed output voltage of 3.2 V, which is used for
powering up the internal RTC. It can also be used for supplying
power to external components, such as a microcontroller.
The maximum current that can be derived from VREGO is 50 mA.
The keep alive LDO stays on even when the ADP5046 is disabled.
Only the UVLO_SYS circuit can disable this regulator. When the
keep alive LDO regulator is disabled and the VREGO is at the
off state, the discharge switch is turned on.

UVLO_SYS CIRCUIT

The UVLO_SYS circuit detects a low supply voltage from the
main battery. The output signal from this circuit enables the
VREGO keep alive LDO circuit and the Channel 1 PSM boost
regulator.
VBATT
REF

UVLO_RTC CIRCUIT

The UVLO_RTC circuit detects a low supply voltage of the RTC
block and the backup registers. When the voltage at the BU3INT
pin falls below the UVLO_RTC threshold, the RTC and the
backup registers are reset.
Rev. Sp0 | Page 23 of 60
ADP50460008
CH 2 CH 3 CH 4 CH 5
Yes Yes Yes No
Yes Yes Yes No
VDD
VDD
VREGO
UVLO_SYS
REF
DISCHARGE
SWITCH
Figure 40. Keep Alive LDO Circuit
VDD
UVLO_SYS TO KEEP ALIVE LDO
TO CHANNEL 1 PSM
Figure 41. UVLO_SYS Circuit
1
CH 6 CH 7 CH 8
Yes No Yes
Yes Yes No