Analog Devices ADP50460008 Owner's Manual page 39

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Address 6—EN_DLY8 (Channel 8 Enable Delay Time Register)
Table 28. Bus Assignment Bit Map
B7 (MSB) B6
EN_DLY8_3 EN_DLY8_2
Table 29. Enable Delay for Channel 8
Bits Description
EN_DLY8_3 Channel 8 enable delay time, 16 ms
EN_DLY8_2 Channel 8 enable delay time, 8 ms
EN_DLY8_1 Channel 8 enable delay time, 4 ms
EN_DLY8_0 Channel 8 enable delay time, 2 ms
Table 30. Channel 8 Enable Delay Time Setting
B7 B6
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Address 7—DIS_DLY3 (Channel 3 Disable Delay Time Register)
Table 31. Bus Assignment Bit Map
B7 (MSB) B6
0 0
Table 32. Channel 3 Disable Delay time
Bits Description
DIS_DLY_2 Channel 3 disable delay time, 120 ms
DIS_DLY_1 Channel 3 disable delay time, 60 ms
DIS_DLY_0 Channel 3 disable delay time, 30 ms
Table 33. Channel 3 Disable Delay Time Settings
Setting
B2 B1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
B5 B4
EN_DLY8_1 EN_DLY8_0
Setting
B5 B4
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
B5 B4
0 0
B0 Disable Delay Time (ms)
0 0
1 30
0 60
1 90
0 120
1 150
0 180
1 210
B3
0
Enable Delay Time (ms)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
B3
0
Rev. Sp0 | Page 39 of 60
ADP50460008
B2 B1
0 0
B2 B1
DIS_DLY_2 DIS_DLY_1
B0 (LSB)
0
B0 (LSB)
DIS_DLY_0