I 2 C Interface Timing Specifications - Analog Devices ADP50460008 Owner's Manual

ADI Confidential
2
I C INTERFACE TIMING SPECIFICATIONS
T = 25°C, V = V = 3.6 V, V
J VBATT VDD
Table 6.
Parameter Min
f
SCL
t 0.6
HIGH
t 1.3
LOW
t 100
SU,DAT
t 0
HD,DAT
t 0.6
SU,STA
t 0.6
HD,STA
t 1.3
BUF
t 0.6
SU,STO
t 20 + 0.1C
R
t 20 + 0.1C
F
t 0
SP
2
C
B
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the
SCL falling edge.
2 B of C is the total capacitance of one bus line in picofarads (pF).
B
Timing Diagram
SDA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
= 3.3 V, unless otherwise noted.
VDDIO
Typ Max
400
0.9
2 300
B
2
300
B
50
400
t
t
LOW
R
t
SU,DAT
t
HD,DAT
Figure 2. I
Unit Description
kHz SCL clock frequency
µs SCL high time
µs SCL low time
ns Data setup time
µs Data hold time
µs Setup time for repeated start
µs Hold time for start or repeated start
µs Bus-free time between a stop condition and a start condition
µs Setup time of a stop condition
ns Rise time of SCL and SDA
ns Fall time of SCL and SDA
ns Pulse width of suppressed spike
pF Capacitive load for each bus line
t
t F
F t
HD,STA
t
SU,STA
t
Sr
HIGH
2 C Interface Timing Diagram
Rev. Sp0 | Page 9 of 60
ADP50460008
1
t
BUF
t
t
R
SP
t
SU,STO
P S