Analog Devices ADP50460008 Owner's Manual page 44

Compact pmu with six dc-to-dc channels, two ldos, load switch, and rtc
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ADP50460008
Address 33 to Address 39—RTCT (Set for Time Registers)
Table 53. Bus Assignment Bit Map for the RTCT Registers
Register
Data Range
RTCT_SEC
0 to 59
RTCT_MIN
0 to 59
RTCT_HR
0 to 23
RTCT_DAY
0 to 30
RTCT_MO
0 to 11
RTCT_YR
0 to 127
RTCT_WK
0 to 6
1
Default value is 01/01/2000 00:00.
2
These registers are backed up with a backup battery. In case of undervoltage lockout of the BU3INT pin, all data is cleared to 0. The read status is assigned to Bit 7
2
(see the I
C Interface section).
Address 40—RTCADJ (RTC Adjust Data Register)
Table 54. Bus Assignment Bit Map
B7 (MSB)
B6
3
RDST_ADJ
ADJS
±
1
The total minimum adjustment value is −61 ppm, and the total maximum adjustment value is +61 ppm.
2
This register is backed up by a backup battery. If an undervoltage lockout of the BU3INT pin occurs, all data is cleared to 0. The read status is assigned to Bit 7 (see the
I
2
C Interface section).
3
The ADJS bit determines if the set adjustment values (shown in parentheses) of Bits[5:0] are added or subtracted to increase or decrease the correction. If Bit 6 is set to 1, the
values of Bits[5:0] that are set to 1 are added; if Bit 6 is set to 0, the values of Bits[5:0] that are set to 1 are subtracted.
Address 41 to Address 43—RTCAL (RTC Countdown Alarm Timer One-Shot Data Registers)
Table 55. Bus Assignment Bit Map
Register
Data Range
RTCAL_SEC
0 to 119
RTCAL_MIN
0 to 59
RTCAL_HR
0 to 31
Address 44 to Address 59—REG0 to REG15 (Configuration Registers)
Table 56. Bus Assignment Bit Map for the Configuration Registers
Register
B7 (MSB)
REG0
RDST_REG0
REG1
RDST_REG1
REG2
RDST_REG2
REG3
RDST_REG3
REG4
RDST_REG4
REG5
RDST_REG5
REG6
RDST_REG6
REG7
RDST_REG7
REG8
RDST_REG8
REG9
RDST_REG9
REG10
RDST_REG10
REG11
RDST_REG11
REG12
RDST_REG12
REG13
RDST_REG13
REG14
RDST_REG14
REG15
RDST_REG15
1
These registers are backed up with a backup battery. In case of undervoltage lockout of the BU3INT pin, all data is cleared to 0. The read status is assigned to Bit 7 (see
2
the I
C Interface section).
B7 (MSB)
B6
B5
RDST_TSEC
0
SEC_5
RDST_TMIN
0
MIN_5
RDST_THR
0
0
RDST_TDAY
0
0
RDST_TMON
0
0
RDST_TYAR
YR_6
YR_5
RDST_TWEK
0
0
1, 2
B5
B4
ADJ_5
ADJ_4
(32 ppm)
(16 ppm)
B7 (MSB)
B6
RDST_ASEC
ASEC_6
RDST_AMIN
0
RDST_AHR
TIMEOUT
B6
B5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. Sp0 | Page 44 of 60
1, 2
B4
B3
SEC_4
SEC_3
MIN_4
MIN_3
HR_4
HR_3
DAY_4
DAY_3
0
MO_3
YR_4
YR_3
0
0
B3
ADJ_3
(8 ppm)
B5
B4
ASEC_5
ASEC_4
AMIN_5
AMIN_4
0
AHR_4
1
B4
B3
0
RG0_3
0
RG1_3
0
RG2_3
0
RG3_3
0
RG4_3
0
RG5_3
0
RG6_3
0
RG7_3
0
RG8_3
0
RG9_3
0
RG10_3
0
RG11_3
0
RG12_3
0
RG13_3
0
RG14_3
0
RG15_3
ADI Confidential
B2
B1
SEC_2
SEC_1
MIN_2
MIN_1
HR_2
HR_1
DAY_2
DAY_1
MO_2
MO_1
YR_2
YR_1
WK_2
WK_1
B2
B1
ADJ_2
ADJ_1
(4 ppm)
(2 ppm)
B3
B2
B1
ASEC_3
ASEC_2
ASEC_1
AMIN_3
AMIN_2
AMIN_1
AHR_3
AHR_2
AHR_1
B2
B1
RG0_2
RG0_1
RG1_2
RG1_1
RG2_2
RG2_1
RG3_2
RG3_1
RG4_2
RG4_1
RG5_2
RG5_1
RG6_2
RG6_1
RG7_2
RG7_1
RG8_2
RG8_1
RG9_2
RG9_1
RG10_2
RG10_1
RG11_2
RG11_1
RG12_2
RG12_1
RG13_2
RG13_1
RG14_2
RG14_1
RG15_2
RG15_1
B0 (LSB)
SEC_0
MIN_0
HR_0
DAY_0
MO_0
YR_0
WK_0
B0 (LSB)
ADJ_0
(1 ppm)
B0 (LSB)
ASEC_0
AMIN_0
AHR_0
B0 (LSB)
RG0_0
RG1_0
RG2_0
RG3_0
RG4_0
RG5_0
RG6_0
RG7_0
RG8_0
RG9_0
RG10_0
RG11_0
RG12_0
RG13_0
RG14_0
RG15_0

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