Analog Devices ADP50460008 Owner's Manual page 28

ADP50460008
Channel 3 Buck Regulator
The Channel 3 buck regulator is a highly efficient, step-down
dc-to-dc converter that utilizes a high speed, fixed-frequency
current mode architecture. No external compensation is needed.
Channel 3 maintains a constant output voltage, regardless of
load, by adjusting the peak inductor current threshold and the
duty cycle of the power switches. At the start of each oscillator
cycle, the PFET switch is turned on, sending a positive voltage
across the inductor. Current in the inductor increases until the
current sense signal crosses the peak inductor current threshold,
which turns off the PFET switch and turns on the NFET synchro-
nous rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle.
Channel 3 has protection circuitry to limit the amount of positive
current flowing through the PFET switch and the synchronous
rectifier. The current limit on the power switch limits the amount
of current that can flow from the input to the output. The output
voltage of Channel 3 is programmable via the I
Table 37 and Table 38).
DISCHARGE
SWITCH
FB3
6C
2 C interface (see
CURRENT SENSE AMP
MAX DUTY
PWM COMP
ERROR AMP
2.5MHz
REF
Figure 50. Channel 3 Buck Regulator Block Diagram
Channel 3 includes an internal soft start function that ramps
the output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery is connected to the input of the converters.
The soft start time can be programmed through the I
and selected from 1.3 ms or 4 ms (see Table 16, Table 17, and
Table 18).
The overvoltage or undervoltage status of each channel can be
read back through the I
The regulator turn-on delay for Channel 3 is controlled by Bits[7:4]
in Register EN_DLY36 at Address 5 (see Table 25, Table 26, and
Table 27). The regulator turn-off delay for Channel 3 is controlled
by Bits[2:0] in Register DIS_DLY3 at Address 7 (see Table 31,
Table 32, and Table 33). The output voltage level for Channel 3
is controlled by Bits[7:4] in Register VID34 at Address 9 (see
Table 37 and Table 38). The undervoltage protection status for
Channel 3 is confirmed by Bit 2 in Register UVPST at Address 12
(see Table 45 and Table 46). The overvoltage protection status
for Channel 3 can be tested by reading Bit 2 in Register OVPST
at Address 13 (see Table 47 and Table 48).
ANTI-SHOOT-
THROUGH
Rev. Sp0 | Page 28 of 60
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2
C interface
2 C interface.
PVIN3
8A
+
Li+
8B
–
PGND3
SW3
7A
7B
PGND3
6A
6B