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ADP50460008
SYSTEM RESET FOR EXTERNAL PROCESSOR (POCO)
The ADP5046 has a low quiescent current power save mode (PSM)
boost regulator to maintain the voltage of the VDD pin above 3.6 V.
Therefore, the keep alive LDO output (VREGO) can consistently
supply a stable 3.2 V to external circuits that are always on, such
as a microprocessor. The POCO signal can be used as a reset
signal to these circuits. The internal POCO comparator monitors
the voltage of the VREGO pin. If V
POCO output is set to high after a 4 ms delay. When the V
voltage falls below 2.6 V, the POCO output immediately goes low.
BACKUP BATTERY CHARGER
The backup battery charger is included to charge the external
backup battery (either a PAS614 from Shoei Co., Ltd. or an
MS614SE from Seiko Instruments Inc. is recommended) or a
super capacitor. The 3 V LDO, located between VREGO and
BU3INT (see Figure 42), regulates the V
The 3 V LDO output is connected to the BU3INT pin through
the PMOS switch, M1. After the V
POCO threshold, the 3 V LDO and the M1 switch are turned
on sequentially with a delay of 4 ms.
VREGO (3.2V)
(3.0V)
VREGO
3V
3V LDO
POCO
VREGO
POCO
V
= 2.8V
TH
COMP
V
= 2.6V
TL
REF
Figure 42. Backup Battery Block Circuit
rises above 2.8 V, the
VREGO
voltage to 3 V.
BU3INT
voltage rises above the
VREGO
BU3INT
M1
BU3INT
VREGO
POCO
DELAY
(4ms)
VDDIO
LEVELSHIFTER
SCL
VDDIO
SDA
VDDIO
REF
1.8V (TYP)
Figure 44. I
VBATT
UVLO_SYS
VREGO
POCO
M1
VREGO
BU3INT
When the V
VBATT
M1 switch are immediately turned off to prevent any discharge
from the backup battery.
BACKUP MEMORY
The ADP5046 includes a 64-bit backup memory that is accessible
2
via the I
C interface. The power source for these registers is the
same as the power source for the RTC. As long as the backup
battery is alive or there is a main power supply, the data in the
backup memory is retained. All data in the backup registers is
cleared when the UVLO_RTC signal goes low.
I
2
C INTERFACE
Access to the internal registers is available using the I
This serial interface has two dedicated pins: SDA, an open-drain
line for receiving and transmitting data; and SCL, an input line
for receiving the clock signal. Both lines must be terminated
with pull-up resistors to the VDDIO supply. Serial data is
transferred at the SCL rising edge. The read data is generated
at the SDA pin in read mode.
VDD
VDDIO
VDD
2
I
C
TRIM DATA
UVLO_VDDIO
2
C Interface Block Diagram
Rev. Sp0 | Page 24 of 60
ADI Confidential
4ms
ON
Figure 43. Backup Battery Charger Timing
voltage falls below 2.4 V, the 3 V LDO and the
VDD
REGISTER
UVLO_SYS
UVP/OVP
4ms
ON
2
C interface.
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