Chapter 3: Connecting and Configuring the Analysis Probe
Connecting the Analysis Probe to the Logic Analyzer
If fewer than eight pods are available for timing, the logic analyzer will
truncate the pods allocated. In this case, viewing the logic analyzer
FORMAT menu shows the pod allocations. If the allocations will not
acquire the desired signals, the allocations can be altered manually.
One- or two-card HP 16554/55/56/57 Timing Connections.
Configuration File (Timing Analysis)
Use configuration files C_33X_2T or C_37X_2T for timing
analysis with the HP 16554/55/56/57 logic analyzers.
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Solutions for CPU32